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A New Design Method for Variable Digital Filter Based on Field Programmable Gate Array(FPGA) 认领 引用 被引量：2
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作者 胡文静 仇润鹤 李外云 《Journal of Donghua University(English Edition)》 EI CAS 2012年第2期193-196,共4页
In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper ... In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method. 展开更多
关键词 variable digital filter(VDF) field programmable gate array(FPGA) embedded micro-processor(EMP)
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A novel fuzzy logic direct torque controller for a permanent magnet synchronous motor with a field programmable gate array 认领 引用 被引量：1
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作者 陈永军 《Journal of Chongqing University》 2008年第3期228-233,共6页
A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchr... A high-performance digital servo system built on the platform of a field programmable gate array (FPGA),a fully digitized hardware design scheme of a direct torque control (DTC) and a low speed permanent magnet synchronous motor (PMSM) is proposed. The DTC strategy of PMSM is described with Verilog hardware description language and is employed on-chip FPGA in accordance with the electronic design automation design methodology. Due to large torque ripples in low speed PMSM,the hysteresis controller in a conventional PMSM DTC was replaced by a fuzzy controller. This FPGA scheme integrates the direct torque controller strategy,the time speed measurement algorithm,the fuzzy regulating technique and the space vector pulse width modulation principle. Experimental results indicate the fuzzy controller can provide a controllable speed at 20 r min-1 and torque at 330 N m with satisfactory dynamic and static performance. Furthermore,the results show that this new control strategy decreases the torque ripple drastically and enhances control performance. 展开更多
关键词 fuzzy control direct torque control field programmable gate array permanent magnet synchronous motor
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Implementation of Dynamic Matrix Control on Field Programmable Gate Array 认领 引用 被引量：1
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作者 兰建 李德伟 +1 位作者 杨楠 席裕庚 《Journal of Shanghai Jiaotong university(Science)》 EI 2011年第4期441-446,共6页
High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the impleme... High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA. 展开更多
关键词 model predictive control(MPC) dynamic matrix control(DMC) quadratic programming(QP) active set programmable logic device field programmable gate array(FPGA)
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Development of a Wireless Capsule Endoscope System Based on Field Programmable Gate Array 认领 引用
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作者 李四青 刘华 《Journal of Shanghai Jiaotong university(Science)》 EI 2017年第2期156-160,共5页
A new modular and programmable wireless capsule endoscope is presented in this paper. The capsule system consumes low power and has small physical size. A new image compression algorithm is presented in this paper to ... A new modular and programmable wireless capsule endoscope is presented in this paper. The capsule system consumes low power and has small physical size. A new image compression algorithm is presented in this paper to reduce power consumption and silicon area. The compression algorithm includes color space transform, uniform quantization, sub-sampling, differential pulse code modulation (DPCM) and Golomb-Rice code. The algorithm is tested in a field programmable gate array (FPGA) development board, and the final result achieves 80% compression rate at 40 dB peak signal to noise ratio (PSNR). The algorithm has high image compression efficiency and low power consumption, compared to other existing works. The system is composed of the following three parts: image capsule endoscope, portable wireless receiver and host computer software. The software and hardware design of the three parts are disscussed in details. © 2017, Shanghai Jiaotong University and Springer-Verlag Berlin Heidelberg. 展开更多
关键词 capsule endoscope portable receiver compression algorithm field programmable gate array(FPGA)
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LightIN:a versatile silicon-integrated photonic field programmable gate array with an intelligent configuration framework for next-generation AI clusters 认领 引用
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作者 Ying Zhu Yifan Liu +14 位作者 Xinyu Yang Kailai Liu Xin Hua Ming Luo Jia Liu Siyao Chang Jie Yan Shengxiang Zhang Miao Wu Zhicheng Wang Hongguang Zhang Dong Wang Daigao Chen Xi Xiao Shaohua Yu 《Light: Science & Applications》 SCIE EI CAS CSCD 2026年第5期1736-1750,共15页
Artificial Intelligence models pose serious challenges to intensive computing and high-bandwidth communication for conventional electronic circuit-based computing clusters.Silicon photonic technologies,due to their hi... Artificial Intelligence models pose serious challenges to intensive computing and high-bandwidth communication for conventional electronic circuit-based computing clusters.Silicon photonic technologies,due to their high speed,low latency,large bandwidth,and complementary metal-oxide-semiconductor compatibility,have been widely implemented for data transmission and actively explored as photonic neural networks in AI clusters.However,current silicon photonic integrated chips lack adaptability for multifunctional use and hardware-software systematic coordination,which is adverse to the development of photo-electronic AI clusters.Here,we develop a reconfigurable silicon photonic chip with 40 programmable unit cells integrating over 160 components,which,to the best of our knowledge,is the first to realize diverse functions for AI clusters with a chip,from computing acceleration and signal processing to network switching and secure encryption.Using a self-developed testing,compilation,and adjustment framework to the chip without in-chip monitoring photodetectors,we have demonstrated(1)4×4 bi-direction unitary and 3×3 uni-direction non-unitary matrix multiplications,achieving a speed of over 1.92 TOPS with 6.22-bit precision and energy efficiency of 1.875 pJ MAC-1,and neural networks for image recognition with a latency of 260 ps;(2)micro-ring modulator wavelength locking in the 5 to 32 Gb s-1 transmission systems;(3)4×4 photonic channel switching with low to-44 dB inter-channel crosstalk;(4)silicon photonic physical unclonable functions.This optoelectronic processing system,incorporating the photonic chip and its software stack,paves the way for both advanced photonic system-on-chip design and the construction of photo-electronic AI clusters. 展开更多
关键词 artificial intelligence models intelligent configuration framework data transmission photonic neural networks photonic technologiesdue silicon integrated photonic field programmable gate array silicon photonic integrated chips intensive computing
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An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays 认领 引用
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作者 Zhen-guo MA Feng YU +1 位作者 Rui-feng GE Ze-ke WANG 《Journal of Zhejiang University-Science C(Computers and Electronics)》 2011年第4期323-329,共7页
We present a novel method to implement the radix-2 fast Fourier transform(FFT)algorithm on field programmable gate arrays(FPGA).The FFT architecture exploits parallelism by having more pipelined units in the stages,an... We present a novel method to implement the radix-2 fast Fourier transform(FFT)algorithm on field programmable gate arrays(FPGA).The FFT architecture exploits parallelism by having more pipelined units in the stages,and more parallel units within a stage.It has the noticeable advantages of high speed and more efficient resource utilization by employing four ganged butterfly engines(GBEs),and can be well matched to the placement of the resources on the FPGA.We adopt the decimation-infrequency(DIF)radix-2 FFT algorithm and implement the FFT processor on a state-of-the-art FPGA.Experimental results show that the processor can compute 1024-point complex radix-2 FFT in about 11μs with a clock frequency of 200 MHz. 展开更多
关键词 Ganged butterfly engine(GBE) Radix-2 Fast Fourier transform(FFT) Field programmable gate array(FPGA)
MIXED-GRAINED CMOS FIELD PROGRAMMABLE ANALOG ARRAY FOR SMART SENSORY APPLICATIONS 认领 引用
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作者 Cheng Xiaoyan Yang Haigang +3 位作者 Yin Tao Wu Qisong Zhi Tian Liu Fei 《Journal of Electronics(China)》 2014年第2期129-142,共14页
The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arr... The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations. 展开更多
关键词 Field Programmable Gate Array(FPGA) Field Programmable Analog Array(FPAA) Sensor Mixed-grained Configurable Analog Block(CAB) Correlated Double Sampling(CDS)
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Programmable array antenna based on nematic liquid crystals for the Ka-band 认领 引用
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作者 WANG Qiang KE Junchen BAI Lin 《Journal of Southeast University(English Edition)》 EI CAS 2025年第1期78-83,共6页
A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a ph... A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a phase shift exceeding 360°with high linearity.First,the above 64 antenna units are periodically arranged into an 8×8 NLC-based antenna array,and the bias voltage of the NLC-based phase shifter loaded on the antenna unit is adjusted through the control of the field-programmable gate array(FPGA)programming sequences.This configuration enables precise phase changes for all 64 channels.Numerical simulation,sample processing,and experimental measurements of the antenna array are conducted to validate the performance of the antenna.The numerical and experimental results demonstrate that the proposed antenna performs well within the frequency range of 19.5-20.5 GHz,with a 3 dB relative bandwidth of 10%and a maximum main lobe gain of 14.1 dBi.A maximum scanning angle of±34°is achieved through the adjustment of the FPGA programming sequence.This NLC-based programmable array antenna shows promising potential for applications in satellite communication. 展开更多
关键词 array antenna nematic liquid crystals electronically beam scanning field programmable gate array(FPGA)
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Implementation of Synchronization Technology in Orthogonal Frequency Division Multiplex System Based on Field Programming Gate Array 认领 引用
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作者 YI Qing-ming XIE Sheng-li 《Semiconductor Photonics and Technology》 2008年第1期32-36,共5页
In this paper,analyzed is the symbol synchronization algorithm in orthogonal frequency division multiplex(OFDM)system,and accomplished are the hardware circuit design of coarse and elaborate synchronization algorithms... In this paper,analyzed is the symbol synchronization algorithm in orthogonal frequency division multiplex(OFDM)system,and accomplished are the hardware circuit design of coarse and elaborate synchronization algorithms.Based on the analysis of coarse and elaborate synchronization algorithms,multiplexed are,the module accumulator,division and output judgement,which can evidently save the hardware resource cost.The analysis of circuit sequence and wave form simulation of the design scheme shows that the proposed method efficiently reduce system resources and power consumption. 展开更多
关键词 orthogonal frequency division multiplex timing synchronization field programmable gate array
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Multi-scroll hopfield neural network excited by memristive self-synapses and its application in image encryption 认领 引用
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作者 Ting He Fei Yu +4 位作者 Yue Lin Shaoqi He Wei Yao Shuo Cai Jie jin 《Chinese Physics B》 SCIE EI CAS CSCD 2025年第12期140-153,共14页
The functionality of the biological brain is closely related to the dynamic behavior generated by synapses in its complex neural system.The self-connection synapse,as a critical form of feedback synapse in Hopfield ne... The functionality of the biological brain is closely related to the dynamic behavior generated by synapses in its complex neural system.The self-connection synapse,as a critical form of feedback synapse in Hopfield neurons,plays an essential role in understanding the dynamic behavior of the brain.Synaptic memristors can bring neural network models closer to the complexity of the brain's neural networks.Inspired by this,this study incorporates the nonlinear memory characteristics of synapses into the Hopfield neural network(HNN)by replacing a single self-synapse in a four-dimensional HNN model with a novel cosine memristor model,aiming to more realistically reproduce the dynamical behavior of biological neurons in artificial systems.By performing a dynamical analysis of the system using numerical methods,we find that the model exhibits infinitely many equilibrium points and can induce the formation of rare transient attractors,as well as an arbitrary number of multi-scroll attractors.Additionally,the model demonstrates complex coexisting attractor dynamics,including transient chaos,periodicity,decaying periodicity,and coexisting chaos.Furthermore,the feasibility of the proposed HNN model is verified using a field-programmable gate array(FPGA).Finally,an electronic codebook(ECB)–mode block cipher encryption algorithm is proposed for image encryption.The encryption performance is evaluated,with an information entropy value of 7.9993,demonstrating the excellent randomness of the system-generated numbers. 展开更多
关键词 self-connected synapses Hopfield neural network multi-scroll attractor field programmable gate array image encryption
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FPGA-Based Efficient Programmable Polyphase FIR Filter 认领 引用 被引量：4
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作者 CHEN He XIONG Cheng-huan +1 位作者 ZHONG Shun-an WANG Hua 《Journal of Beijing Institute of Technology》 EI CAS 2005年第1期4-8,共5页
The modelling,design and implementation of a high-speed programmable polyphase finite impulse response(FIR)filter with field programmable gate array(FPGA)technology are described.This FIR filter can run automatically ... The modelling,design and implementation of a high-speed programmable polyphase finite impulse response(FIR)filter with field programmable gate array(FPGA)technology are described.This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry,odd/even taps,from 32 taps up to 256 taps.The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of(160 MHz.) 展开更多
关键词 finite impulse response(FIR)filter polyphase field programmable gate array(FPGA)
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Low power Viterbi decoder design for low altitude adhoc networks 认领 引用
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作者 FEI Yingying XIAO Chunlu +3 位作者 JING Wenhao MA Tianming WANG Jiahan JIN Jie 《High Technology Letters》 EI CAS 2025年第2期154-163,共10页
With the rapid development of low altitude economic industry,low altitude adhoc network technology has been getting more and more intensive attention.In the adhoc network protocol designed in this paper,the convolutio... With the rapid development of low altitude economic industry,low altitude adhoc network technology has been getting more and more intensive attention.In the adhoc network protocol designed in this paper,the convolutional code used is(3,1,7),and the design of a low power Viterbi decoder adapted to multi-rate variations is proposed.In the traditional Viterbi decoding method,the high complexity of path metric(PM)accumulation and Euclidean distance computation leads to the problems of low efficiency and large storage resources in the decoder.In this paper,an improved add compare select(ACS)algorithm,a generalized formula for branch metric(BM)based on Manhattan distance,and a method to reduce the accumulated PM for different Viterbi decoders are put forward.A simulation environment based on Vivado and Matlab to verify the accuracy and effectiveness of the proposed Viterbi decoder is also established.The experimental results show that the total power consumption is reduced by 15.58%while the decoding accuracy of the Viterbi decoder is guaranteed,which meets the design requirements of a low power Viterbi decoder. 展开更多
关键词 low altitude adhoc network Manhattan distance network protocol Viterbi decoder field programmable gate array(FPGA)
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Design of Parallel Electrical Resistance Tomography System for Measuring Multiphase Flow 认领 引用 被引量：7
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作者 董峰 许聪 +1 位作者 张志强 任尚杰 《Chinese Journal of Chemical Engineering》 SCIE EI CAS CSCD 2012年第2期368-379,共12页
ERT(electrical resistance tomography) is effective method for visualization of multiphase flows,offering some advantages of rapid response and low cost,so as to explore the transient hydrodynamics.Aiming at this targe... ERT(electrical resistance tomography) is effective method for visualization of multiphase flows,offering some advantages of rapid response and low cost,so as to explore the transient hydrodynamics.Aiming at this target,a fully programmable and reconfigurable FPGA(field programmable gate array)-based Compact PCI(peripheral component interconnect) bus linked sixteen-channel ERT system has been presented.The data acquisition system is carefully designed with function modules of signal generator module;Compact PCI transmission module and data processing module(including data sampling,filtering and demodulating).The processing module incorporates a powerful FPGA with Compact PCI bus for communication,and the measurement process management is conducted in FPGA.Image reconstruction algorithms with different speed and accuracy are also coded for this system.The system has been demonstrated in real time(1400 frames per second for 50 kHz excitation) with signal-noise-ratio above 62 dB and repeatability error below 0.7%.Static experiments have been conducted and the images manifested good resolution relative to the actual object distribution.The parallel ERT system has provided alternative experimental platform for the multiphase flow measurements by the dynamic experiments in terms of concentration and velocity. 展开更多
关键词 electrical resistance tomography data acquisition compact peripheral component interconnect field programmable gate array digital filter digital demodulation
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GF-3 data real-time processing method based on multi-satellite distributed data processing system 认领 引用 被引量：7
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作者 YANG Jun CAO Yan-dong +2 位作者 SUN Guang-cai XING Meng-dao GUO Liang 《Journal of Central South University》 SCIE EI CAS CSCD 2020年第3期842-852,共11页
Due to the limited scenes that synthetic aperture radar(SAR)satellites can detect,the full-track utilization rate is not high.Because of the computing and storage limitation of one satellite,it is difficult to process... Due to the limited scenes that synthetic aperture radar(SAR)satellites can detect,the full-track utilization rate is not high.Because of the computing and storage limitation of one satellite,it is difficult to process large amounts of data of spaceborne synthetic aperture radars.It is proposed to use a new method of networked satellite data processing for improving the efficiency of data processing.A multi-satellite distributed SAR real-time processing method based on Chirp Scaling(CS)imaging algorithm is studied in this paper,and a distributed data processing system is built with field programmable gate array(FPGA)chips as the kernel.Different from the traditional CS algorithm processing,the system divides data processing into three stages.The computing tasks are reasonably allocated to different data processing units(i.e.,satellites)in each stage.The method effectively saves computing and storage resources of satellites,improves the utilization rate of a single satellite,and shortens the data processing time.Gaofen-3(GF-3)satellite SAR raw data is processed by the system,with the performance of the method verified. 展开更多
关键词 synthetic aperture radar full-track utilization rate distributed data processing CS imaging algorithm field programmable gate array Gaofen-3
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高分辨中子闪烁体探测器读出电子学研制 认领 引用 被引量：6
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作者 周诗慧 黄河 +12 位作者 万志永 陈少佳 朱志甫 唐彬 黄畅 王修库 曾莉欣 于莉 杨浩 刘慧银 岳秀萍 赵豫斌 孙志嘉 《核技术》 CAS CSCD 北大核心 2023年第11期30-39,共10页
能量分辨中子成像谱仪是中国散裂中子源当前在建的谱仪之一,其衍射探测器90°分区采用6LiF/ZnS中子闪烁体探测器作为探测设备。为实现探测器高位置分辨,读出电子学系统采用了一种电容网络复合读出电路和电荷重心法相结合的实现方法... 能量分辨中子成像谱仪是中国散裂中子源当前在建的谱仪之一,其衍射探测器90°分区采用6LiF/ZnS中子闪烁体探测器作为探测设备。为实现探测器高位置分辨,读出电子学系统采用了一种电容网络复合读出电路和电荷重心法相结合的实现方法,并研制了电子学样机。该样机由电容网络复合读出电路、前置放大板和数字读出板三部分组成,基本功能验证完成后,分别在实验室和中国散裂中子源的20号束线上进行了相关性能参数测试,测试结果显示:电子学的积分非线性≤0.95%,时间分辨约为12 ns;探测器位置分辨为1 mm、探测效率为65%@1.6?,均达到了工程设计指标。该样机的成功研制为能量分辨中子成像谱仪未来顺利开展谱仪实验提供了可靠的技术保障。 展开更多
关键词 电容网络 中子闪烁体探测器 硅光电倍增管 电荷重心法 可编程门阵列(Field Programmable Gate Array FPGA)
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REVIEW OF ADVANCED FPGA ARCHITECTURES AND TECHNOLOGIES 认领 引用 被引量：8
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作者 Yang Haigang Zhang Jia +1 位作者 Sun Jiabin Yu Le 《Journal of Electronics(China)》 2014年第5期371-393,共23页
Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid developme... Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development. 展开更多
关键词 Field Programmable Gate Array(FPGA) Microchip architecture Programmable logic device System-on-Chip(SoC)
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基于Xilinx型FPGA系统单粒子效应评估方法研究 认领 引用 被引量：3
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作者 王鹏 邹彬 +1 位作者 刘金枝 周丹阳 《电子学报》 EI CAS CSCD 北大核心 2022年第11期2716-2721,共6页
Virtex-5系列芯片没有官方提供的专用软错误缓解(Soft Error Mitigation,SEM)IP核,需自行设计故障注入系统.本文选用XC5VFX130T型现场可编程门阵列(Field Programmable Gate Array,FPGA)芯片利用单帧部分重构功能达到等同于SEM IP故障... Virtex-5系列芯片没有官方提供的专用软错误缓解(Soft Error Mitigation,SEM)IP核,需自行设计故障注入系统.本文选用XC5VFX130T型现场可编程门阵列(Field Programmable Gate Array,FPGA)芯片利用单帧部分重构功能达到等同于SEM IP故障注入效果,实现对FPGA电路系统的抗单粒子翻转能力评估测试.利用逐位注入故障模式对XC5VFX130T型FPGA的配置位逐个注入故障,获得待评估电路的敏感配置位信息;对待测电路进行三模冗余防护加固,利用累积故障注入模式连续随机注入模拟单粒子辐照试验环境,得到待评估电路的功能中断截面,进而实现对基于XC5VFX130T型FPGA系统的抗单粒子翻转加固效果的评估.研究表明,基准电路(移位寄存器链等)评估得到的功能中断截面与实际辐照试验中的功能中断截面曲线变化一致,为机载电子的单粒子效应适航评估提供了支持. 展开更多
关键词 FPGA(Field Programmable Gate Array) 部分重构 单粒子翻转 逐位注入 三模冗余 累积故障注入 功能中断截面
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High Precision Absolute Gravity Meter Based on Time-to-Digital Conversion in FPGA 认领 引用 被引量：3
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作者 LIU Sanjun YANG Junhong CHEN Hao 《Wuhan University Journal of Natural Sciences》 CAS CSCD 2021年第4期358-364,共7页
This paper proposes a novel method to design a high precision portable gravity acceleration meter on the Field Programmable Gate Array(FPGA)platform.Two technologies are used in FPGA to improve the time measurement ac... This paper proposes a novel method to design a high precision portable gravity acceleration meter on the Field Programmable Gate Array(FPGA)platform.Two technologies are used in FPGA to improve the time measurement accuracy to 54 ps and the measurement accuracy of g to the level of 1μGal(1 Gal=1 cm/s2).The one is the proposed clock rising edge counting method for measuring the coarse time,in which the measured coarse time resolution can reach 5 ns by setting the clock frequency up to 200 MHz.The other is the realization of the time-to-digital conversion(TDC)circuits in FPGA which can further improve the time measurement accuracy to 54 ps.In the TDC circuit,we analyze the influence of the frequency stability of crystal oscillator and the distance of infrared tube on the measurement accuracy of g.The increase of frequency stability(10–9to 10–11)can greatly improve the measurement accuracy of g(5.8143 to 2.0799μGal),but further increase of frequency stability(10–11to 10–12)has little effect on improving the accuracy of g.Through analysis and simulation,it is found that the setting of distance between laser pair also has a great influence on the accuracy of g.Only when the distance is set to the optimal,we can make the accuracy of g the highest.In this paper,the method of obtaining the best distance and the corresponding accuracy of g are given.In addition,the proposed system uses Nios II soft core processor to implement all the controlling,calculation and display functions,which improves system integration,reduces system cost and meets the needs of field geological survey and gravity prospecting. 展开更多
关键词 Field Programmable Gate Array(FPGA) gravity acceleration meter time-to-digital conversion(TDC)
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FPGA implementation of bit-stream neuron and perceptron based on sigma delta modulation 认领 引用 被引量：2
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作者 梁勇 王志功 +1 位作者 孟桥 郭晓丹 《Journal of Southeast University(English Edition)》 EI CAS 2012年第3期282-286,共5页
To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network（ANN） hardware implementation methods,a bit-stream ANN hardware implementation method based on sigma delta（Σ... To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network（ANN） hardware implementation methods,a bit-stream ANN hardware implementation method based on sigma delta（ΣΔ） modulation is presented.The bit-stream adder,multiplier,threshold function unit and fully digital ΣΔ modulator are implemented in a field programmable gate array（FPGA）,and these bit-stream arithmetical units are employed to build the bit-stream artificial neuron.The function of the bit-stream artificial neuron is verified through the realization of the logic function and a linear classifier.The bit-stream perceptron based on the bit-stream artificial neuron with the pre-processed structure is proved to have the ability of nonlinear classification.The FPGA resource utilization of the bit-stream artificial neuron shows that the bit-stream ANN hardware implementation method can significantly reduce the demand of the ANN hardware resources. 展开更多
关键词 bit-stream artificial neuron perceptron sigma delta field programmable gate array（FPGA）
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A multi-directional controllable multi-scroll conservative chaos generator:Modelling,analysis,and FPGA implementation 认领 引用 被引量：2
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作者 En-Zeng Dong Rong-Hao Li Sheng-Zhi Du 《Chinese Physics B》 SCIE EI CAS CSCD 2021年第2期232-239,共8页
Combing with the generalized Hamiltonian system theory,by introducing a special form of sinusoidal function,a class of n-dimensional(n=1,2,3)controllable multi-scroll conservative chaos with complicated dynamics is co... Combing with the generalized Hamiltonian system theory,by introducing a special form of sinusoidal function,a class of n-dimensional(n=1,2,3)controllable multi-scroll conservative chaos with complicated dynamics is constructed.The dynamics characteristics including bifurcation behavior and coexistence of the system are analyzed in detail,the latter reveals abundant coexisting flows.Furthermore,the proposed system passes the NIST tests and has been implemented physically by FPGA.Compared to the multi-scroll dissipative chaos,the experimental portraits of the proposed system show better ergodicity,which have potential application value in secure communication and image encryption. 展开更多
关键词 multi-directional controllable multi-scroll conservative chaos coexisting flows field programmable gate array(FPGA)
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