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Resonance Characteristics of Piezoelectric Resonator Based on Digital Driving Circuit of Field-Programmable Gate Array 认领 引用 被引量：2
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作者 WANG Zhenyu WU Xiaosheng SHU Shengzhu 《Journal of Shanghai Jiaotong university(Science)》 EI 2019年第1期1-6,共6页
Piezoelectric resonators are widely used in frequency reference devices, mass sensors, resonant sensors(such as gyros and accelerometers), etc. Piezoelectric resonators usually work in a special resonant mode. Obtaini... Piezoelectric resonators are widely used in frequency reference devices, mass sensors, resonant sensors(such as gyros and accelerometers), etc. Piezoelectric resonators usually work in a special resonant mode. Obtaining working resonant mode with high quality is key to improve the performance of piezoelectric resonators. In this paper, the resonance characteristics of a rectangular lead zirconium titanate(PZT) piezoelectric resonator are studied. On the basis of the field-programmable gate array(FPGA) embedded system, direct digital synthesizer(DDS) and automatic gain controller(AGC) are used to generate the driving signals with precisely adjustable frequency and amplitude. The driving signals are used to excite the piezoelectric resonator to the working vibration mode. The influence of the connection of driving electrodes and voltage amplitude on the vibration of the resonator is studied. The quality factor and vibration linearity of the resonator are studied with various driving methods mentioned in this paper. The resonator reaches resonant mode at 330 kHz by different driving methods.The relationship between resonant amplitude and driving signal amplitude is linear. The quality factor reaches over 150 by different driving methods. The results provide a theoretical reference for the efficient excitation of the piezoelectric resonator. 展开更多
关键词 piezoelectric resonators resonant mode quality factor linearity field-programmable gate array(FPGA)
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A New Design Method for Variable Digital Filter Based on Field Programmable Gate Array(FPGA) 认领 引用 被引量：2
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作者 胡文静 仇润鹤 李外云 《Journal of Donghua University(English Edition)》 EI CAS 2012年第2期193-196,共4页
In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper ... In order to obtain variable characteristics,the digital filter's type,number of taps and coefficients should be changed constantly such that the desired frequency-domain characteristics can be obtained.This paper proposes a method for self-programmable variable digital filter(VDF) design based on field programmable gate array(FPGA).We implement a digital filter system by using custom embedded micro-processor,programmable finite impulse response(P-FIR) macro module,coefficient-loader,clock manager and analog/digital(A/D) or digital/analog(D/A) controller and other modules.The self-programmable VDF can provide the best solution for realization of digital filter algorithms,which are the low-pass,high-pass,band-pass and band-stop filter algorithms with variable frequency domain characteristics.The design examples with minimum 1 to maximum 32 taps FIR filter,based on Modelsim post-routed simulation and onboard running on XUPV5-LX110T,are provided to demonstrate the effectiveness of the proposed method. 展开更多
关键词 variable digital filter(VDF) field programmable gate array(FPGA) embedded micro-processor(EMP)
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Efficientmapping and flexible interconnects:accelerating 3D CNN-based lung nodule segmentation and classification on multi-FPGA 认领 引用
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作者 Zhuang CAO Tian ZHANG +2 位作者 Xiaowei HE Sheng LIU Junzhong SHEN 《ENGINEERING Information Technology & Electronic Engineering》 SCIE EI CSCD 2026年第6期20-41,共22页
Three-dimensional convolutional neural networks(3D CNNs)show considerable promise for lung nodule detection.However,their high computational complexity and memory demands present substantial challenges for acceleratio... Three-dimensional convolutional neural networks(3D CNNs)show considerable promise for lung nodule detection.However,their high computational complexity and memory demands present substantial challenges for acceleration on a single field-programmable gate array(FPGA).To address this,we propose efficient mapping schemes for a multi-FPGA platform,leveraging its massive parallelism to maximize computational efficiency.Our system,integrating six customized FPGA boards,achieves state-of-the-art performance,delivering approximately 15.9 tera operations per second(TOPS)for nodule segmentation and approximately 3.8 TOPS for nodule classification.Compared to a central processing unit baseline,it achieves a 128.2×speedup while exhibiting 6.7×higher energy efficiency than a graphics processing unit implementation.Furthermore,the system attains a state-of-the-art recall rate of 87.1%on the real-world clinical benchmark. 展开更多
关键词 Lung nodule detection Three-dimensional convolutional neural networks(3D CNNs) Field-programmable gate array(FPGA) Multi-FPGA systems Hardware acceleration Parallel mapping
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Synthesis of Nonlinear Control of Switching Topologies of Buck-Boost Converter Using Fuzzy Logic on Field Programmable Gate Array (FPGA) 认领 引用 被引量：1
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作者 Johnson A. Asumadu Vaidhyanathan Jagannathan Arkhom Chachavalnanont 《Journal of Intelligent Learning Systems and Applications》 2010年第1期36-42,共7页
An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the conv... An intelligent fuzzy logic inference pipeline for the control of a dc-dc buck-boost converter was designed and built using a semi-custom VLSI chip. The fuzzy linguistics describing the switching topologies of the converter was mapped into a look-up table that was synthesized into a set of Boolean equations. A VLSI chip–a field programmable gate array (FPGA) was used to implement the Boolean equations. Features include the size of RAM chip independent of number of rules in the knowledge base, on-chip fuzzification and defuzzification, faster response with speeds over giga fuzzy logic inferences per sec (FLIPS), and an inexpensive VLSI chip. The key application areas are: 1) on-chip integrated controllers;and 2) on-chip co-integration for entire system of sensors, circuits, controllers, and detectors for building complete instrument systems. 展开更多
关键词 Multi-Fuzzy Logic Controller (MFLC) Field Programmable Gate Array (FPGA) Buck-Boost Converter Boolean Look-Up Table Co-Integration
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Implementation of Dynamic Matrix Control on Field Programmable Gate Array 认领 引用 被引量：1
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作者 兰建 李德伟 +1 位作者 杨楠 席裕庚 《Journal of Shanghai Jiaotong university(Science)》 EI 2011年第4期441-446,共6页
High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the impleme... High performance computer is often required by model predictive control(MPC) systems due to the heavy online computation burden.To extend MPC to more application cases with low-cost computation facilities, the implementation of MPC controller on field programmable gate array(FPGA) system is studied.For the dynamic matrix control(DMC) algorithm,the main design idea and the implemental strategy of DMC controller are introduced based on a FPGA’s embedded system.The performance tests show that both the computation efficiency and the accuracy of the proposed controller can be satisfied due to the parallel computing capability of FPGA. 展开更多
关键词 model predictive control(MPC) dynamic matrix control(DMC) quadratic programming(QP) active set programmable logic device field programmable gate array(FPGA)
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Fault Prediction and Diagnosis of Warship Equipment Field Programmable Gate Array Software 认领 引用
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作者 LIU Bojiang YAN Ran +2 位作者 CHAI Haiyan HAN Xinyu TANG Longli 《Journal of Donghua University(English Edition)》 CAS 2018年第5期426-429,共4页
In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-dep... In order to solve the current high failure rate of warship equipment field programmable gate array( FPGA) software,fault detection is not timely enough and FPGA detection equipment is expensive and so on. After in-depth research,this paper proposes a warship equipment FPGA software based on Xilinx integrated development environment( ISE) and ModelSim software.Functional simulation and timing simulation to verify the correctness of the logic design of the FPGA,this method is very convenient to view the signal waveform inside the FPGA program to help FPGA test engineers to achieve FPGA fault prediction and diagnosis. This test method has important engineering significance for the upgrading of warship equipment. 展开更多
关键词 Field Programmable Gate Array(FPGA) fault prediction diagnosis
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Development of a Wireless Capsule Endoscope System Based on Field Programmable Gate Array 认领 引用
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作者 李四青 刘华 《Journal of Shanghai Jiaotong university(Science)》 EI 2017年第2期156-160,共5页
A new modular and programmable wireless capsule endoscope is presented in this paper. The capsule system consumes low power and has small physical size. A new image compression algorithm is presented in this paper to ... A new modular and programmable wireless capsule endoscope is presented in this paper. The capsule system consumes low power and has small physical size. A new image compression algorithm is presented in this paper to reduce power consumption and silicon area. The compression algorithm includes color space transform, uniform quantization, sub-sampling, differential pulse code modulation (DPCM) and Golomb-Rice code. The algorithm is tested in a field programmable gate array (FPGA) development board, and the final result achieves 80% compression rate at 40 dB peak signal to noise ratio (PSNR). The algorithm has high image compression efficiency and low power consumption, compared to other existing works. The system is composed of the following three parts: image capsule endoscope, portable wireless receiver and host computer software. The software and hardware design of the three parts are disscussed in details. © 2017, Shanghai Jiaotong University and Springer-Verlag Berlin Heidelberg. 展开更多
关键词 capsule endoscope portable receiver compression algorithm field programmable gate array(FPGA)
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Programmable array antenna based on nematic liquid crystals for the Ka-band 认领 引用
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作者 WANG Qiang KE Junchen BAI Lin 《Journal of Southeast University(English Edition)》 EI CAS 2025年第1期78-83,共6页
A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a ph... A programmable low-profile array antenna based on nematic liquid crystals(NLCs)is proposed.Each antenna unit comprises a square patch radiating structure and a tunable NLC-based phase shifter capable of achieving a phase shift exceeding 360°with high linearity.First,the above 64 antenna units are periodically arranged into an 8×8 NLC-based antenna array,and the bias voltage of the NLC-based phase shifter loaded on the antenna unit is adjusted through the control of the field-programmable gate array(FPGA)programming sequences.This configuration enables precise phase changes for all 64 channels.Numerical simulation,sample processing,and experimental measurements of the antenna array are conducted to validate the performance of the antenna.The numerical and experimental results demonstrate that the proposed antenna performs well within the frequency range of 19.5-20.5 GHz,with a 3 dB relative bandwidth of 10%and a maximum main lobe gain of 14.1 dBi.A maximum scanning angle of±34°is achieved through the adjustment of the FPGA programming sequence.This NLC-based programmable array antenna shows promising potential for applications in satellite communication. 展开更多
关键词 array antenna nematic liquid crystals electronically beam scanning field programmable gate array(FPGA)
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FPGA-based design of laser gyro signal acquisition circuit 认领 引用
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作者 CHEN Jing LI Jinming 《Journal of Measurement Science and Instrumentation》 CAS CSCD 2025年第1期107-118,共12页
With the continuous evolution of electronic technology,field-programmable gate array(FPGA)has demonstrated significant advantages in the realm of signal acquisition and processing,and signal acquisition plays a pivota... With the continuous evolution of electronic technology,field-programmable gate array(FPGA)has demonstrated significant advantages in the realm of signal acquisition and processing,and signal acquisition plays a pivotal role in the practical applications of laser gyros.By analysis of the output signals from a laser gyro and an accelerometer,this paper presents a circuit design for signal acquisition of the laser gyro based on domestic devices.The design incorporates a finite impulse response(FIR)filter to process the gyro signal and employs a small-volume,impact-resistant quartz flexible accelerometer for signal aquisition.Simulation results demonstrate that the errors in X,Y,and Z axes fall within acceptable ranges while meeting filtering requirements.The use of FPGA for signal acquisition and preprocessing enhances configuration flexibility,which provides an idea and method for optimizing performance and processing signals in laser gyro applications. 展开更多
关键词 laser gyro signal acquisition field-programmable gate array(FPGA) finite impulse response(FIR)filter accelerometer
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Searching for complete set of free resource rectangles on FPGA area based on CPTR 认领 引用 被引量：3
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作者 柴亚辉 沈文枫 +2 位作者 徐炜民 刘觉夫 郑衍衡 《Journal of Shanghai University(English Edition)》 2011年第5期391-396,共6页
As a coprocessor, field-programmable gate array （FPGA） is the hardware computing processor accelerating the computing capacity of coraputers. To efficiently manage the hardware free resources for the placing of task... As a coprocessor, field-programmable gate array （FPGA） is the hardware computing processor accelerating the computing capacity of coraputers. To efficiently manage the hardware free resources for the placing of tasks on FPGA and take full advantage of the partially reconfigurable units, good utilization of chip resources is an important and necessary work. In this paper, a new method is proposed to find the complete set of maximal free resource rectangles based on the cross point of edge lines of running tasks on FPGA area, and the prove process is provided to make sure the correctness of this method. 展开更多
关键词 field-programmable gate array （FPGA） partially dynamic reconfigure maximal free rectangle occupied rectangle
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Signal processing circuit of laser gyro based on FPGA and DSP 认领 引用
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作者 张永瑞 苏树清 +1 位作者 冉自博 刘红雨 《Journal of Measurement Science and Instrumentation》 CAS 2013年第2期158-162,共5页
This is a paper about laser gyro sign a l processing circuit which is designed based on field-programmable gate array(FPGA) and digital signal processor(DSP).Through a pre-amplifier circuit,FPGA and DSP,a weak current... This is a paper about laser gyro sign a l processing circuit which is designed based on field-programmable gate array(FPGA) and digital signal processor(DSP).Through a pre-amplifier circuit,FPGA and DSP,a weak current signal is converted and transferred,then sent to the computer to display the final results.Through the laser gyro performance te sting,the obtained results coincide with those of the existing methods.Thus th e d esigned circuit realizes the function of laser gyro signal processing. 展开更多
关键词 laser gyro signal processing field-programmable gate array （FPGA） digital signal processor （DSP） finite impulse response （FIR） filter
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Efficient multiuser detector based on box-constrained deregularization and its FPGA design 认领 引用
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作者 Zhi Quan Jie Liu 《Journal of Systems Engineering and Electronics》 SCIE EI CSCD 2012年第2期179-187,共9页
Multiuser detection can be described as a quadratic optimization problem with binary constraint. Many techniques are available to find approximate solution to this problem. These tech- niques can be characterized in t... Multiuser detection can be described as a quadratic optimization problem with binary constraint. Many techniques are available to find approximate solution to this problem. These tech- niques can be characterized in terms of complexity and detection performance. The ＂efficient frontier＂ of known techniques include the decision-feedback, branch-and-bound and probabilistic data association detectors. The presented iterative multiuser detection technique is based on joint deregularized and box-constrained so- lution to quadratic optimization with iterations similar to that used in the nonstationary Tikhonov iterated algorithm. The deregulari- zation maximizes the energy of the solution, this is opposite to the Tikhonov regularization where the energy is minimized. However, combined with box-constraints, the deregularization forces the solution to be close to the binary set. We further exploit the box- constrained dichotomous coordinate descent （DCD） algorithm and adapt it to the nonstationary iterative Tikhonov regularization to present an efficient detector. As a result, the worst-case and aver- age complexity are reduced down to K28 and K2~ floating point operation per second, respectively. The development improves the ＂efficient frontier＂ in multiuser detection, which is illustrated by simulation results. Finally, a field programmable gate array （FPGA） design of the detector is presented. The detection performance obtained from the fixed-point FPGA implementation shows a good match to the floating-point implementation. 展开更多
关键词 multiuser detection dichotomous coordinate descent （DCD） box-constrained DCD deregularization Tikhonov regular- ization low complexity field-programmable gate array （FPGA）.
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Implementation of encoder and decoder for LDPC codes based on FPGA 认领 引用 被引量：7
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作者 CHENG Kun SHEN Qi +1 位作者 LIAO Shengkai PENG Chengzhi 《Journal of Systems Engineering and Electronics》 SCIE CSCD 2019年第4期642-650,共9页
This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diago... This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA. 展开更多
关键词 low-density parity-check(LDPC) field programmable gate array(FPGA) normalized min-sum algorithm(NMSA).
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REVIEW OF ADVANCED FPGA ARCHITECTURES AND TECHNOLOGIES 认领 引用 被引量：8
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作者 Yang Haigang Zhang Jia +1 位作者 Sun Jiabin Yu Le 《Journal of Electronics(China)》 2014年第5期371-393,共23页
Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid developme... Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development. 展开更多
关键词 Field Programmable Gate Array(FPGA) Microchip architecture Programmable logic device System-on-Chip(SoC)
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基于DSP与FPGA的变流器通用控制平台研究 认领 引用 被引量：15
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作者 郭巍 肖遥 孙永佳 《电气传动》 北大核心 2014年第2期22-26,共5页
提出一种基于DSP和现场可编程门阵列(FPGA)双CPU结构的新型变流器控制系统方案,其中DSP完成变流器控制策略的实现,主要包括:最大功率点跟踪、电压电流双闭环控制、低电压穿越控制、通信功能;FPGA完成三相锁相环控制、AD芯片采样控制、SV... 提出一种基于DSP和现场可编程门阵列(FPGA)双CPU结构的新型变流器控制系统方案,其中DSP完成变流器控制策略的实现,主要包括:最大功率点跟踪、电压电流双闭环控制、低电压穿越控制、通信功能;FPGA完成三相锁相环控制、AD芯片采样控制、SVPWM波形控制、逻辑输出控制以及各类故障信号检测与停机保护功能,并采用了基于WIFI模块的风电故障信息传输系统。以双馈风电变流器为模型,设计了双馈风力发电变流器系统,完成了两电平与三电平SVPWM控制算法的FPGA实现。最后在自主研发的1.5 MW,2 MW双馈式变流器样机与光伏逆变器样机上进行了大量实验和长期的现场试运行,验证了控制系统平台的可行性与实用性。 展开更多
关键词 双PWM变流器 矢量控制 数字信号处理器 现场可编程门阵列 digital signal processor (DSP) field programmable gate array (FPGA)
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FPGA-Based Efficient Programmable Polyphase FIR Filter 认领 引用 被引量：4
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作者 CHEN He XIONG Cheng-huan +1 位作者 ZHONG Shun-an WANG Hua 《Journal of Beijing Institute of Technology》 EI CAS 2005年第1期4-8,共5页
The modelling,design and implementation of a high-speed programmable polyphase finite impulse response(FIR)filter with field programmable gate array(FPGA)technology are described.This FIR filter can run automatically ... The modelling,design and implementation of a high-speed programmable polyphase finite impulse response(FIR)filter with field programmable gate array(FPGA)technology are described.This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry,odd/even taps,from 32 taps up to 256 taps.The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of(160 MHz.) 展开更多
关键词 finite impulse response(FIR)filter polyphase field programmable gate array(FPGA)
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基于Xilinx型FPGA系统单粒子效应评估方法研究 认领 引用 被引量：3
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作者 王鹏 邹彬 +1 位作者 刘金枝 周丹阳 《电子学报》 EI CAS CSCD 北大核心 2022年第11期2716-2721,共6页
Virtex-5系列芯片没有官方提供的专用软错误缓解(Soft Error Mitigation,SEM)IP核,需自行设计故障注入系统.本文选用XC5VFX130T型现场可编程门阵列(Field Programmable Gate Array,FPGA)芯片利用单帧部分重构功能达到等同于SEM IP故障... Virtex-5系列芯片没有官方提供的专用软错误缓解(Soft Error Mitigation,SEM)IP核,需自行设计故障注入系统.本文选用XC5VFX130T型现场可编程门阵列(Field Programmable Gate Array,FPGA)芯片利用单帧部分重构功能达到等同于SEM IP故障注入效果,实现对FPGA电路系统的抗单粒子翻转能力评估测试.利用逐位注入故障模式对XC5VFX130T型FPGA的配置位逐个注入故障,获得待评估电路的敏感配置位信息;对待测电路进行三模冗余防护加固,利用累积故障注入模式连续随机注入模拟单粒子辐照试验环境,得到待评估电路的功能中断截面,进而实现对基于XC5VFX130T型FPGA系统的抗单粒子翻转加固效果的评估.研究表明,基准电路(移位寄存器链等)评估得到的功能中断截面与实际辐照试验中的功能中断截面曲线变化一致,为机载电子的单粒子效应适航评估提供了支持. 展开更多
关键词 FPGA(Field Programmable Gate Array) 部分重构 单粒子翻转 逐位注入 三模冗余 累积故障注入 功能中断截面
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Implementation of motion estimator algorithm with 1/4 pixel accuracy based on FPGA 认领 引用
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作者 向厚振 王鹏 +1 位作者 姚娟 张志杰 《Journal of Measurement Science and Instrumentation》 CAS 2012年第4期341-344,共4页
After research on the motion estimation algorithm in video coding, a motion estimator algorithm with 1/4 pixel ac- curacy is implemented based on fie/d-programmable gate array （FPGA）. The motion estimation algorithm... After research on the motion estimation algorithm in video coding, a motion estimator algorithm with 1/4 pixel ac- curacy is implemented based on fie/d-programmable gate array （FPGA）. The motion estimation algorithm module is made up of the 1[4 pixel interpolation module with serial input and parallel output, the three step search module and the block match- ing module, which can use relatively less Wiener filters for interpolation operation. Experiment results show that the hard- ware design has less consumption of the logical resource, higher stability and lower power consumption. 展开更多
关键词 H. 264/AVC 1/4 pixel three-step search motion estimation field-programmable gate array （FPGA）
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FPGA implementation of bit-stream neuron and perceptron based on sigma delta modulation 认领 引用 被引量：2
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作者 梁勇 王志功 +1 位作者 孟桥 郭晓丹 《Journal of Southeast University(English Edition)》 EI CAS 2012年第3期282-286,共5页
To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network（ANN） hardware implementation methods,a bit-stream ANN hardware implementation method based on sigma delta（Σ... To solve the excessive huge scale problem of the traditional multi-bit digital artificial neural network（ANN） hardware implementation methods,a bit-stream ANN hardware implementation method based on sigma delta（ΣΔ） modulation is presented.The bit-stream adder,multiplier,threshold function unit and fully digital ΣΔ modulator are implemented in a field programmable gate array（FPGA）,and these bit-stream arithmetical units are employed to build the bit-stream artificial neuron.The function of the bit-stream artificial neuron is verified through the realization of the logic function and a linear classifier.The bit-stream perceptron based on the bit-stream artificial neuron with the pre-processed structure is proved to have the ability of nonlinear classification.The FPGA resource utilization of the bit-stream artificial neuron shows that the bit-stream ANN hardware implementation method can significantly reduce the demand of the ANN hardware resources. 展开更多
关键词 bit-stream artificial neuron perceptron sigma delta field programmable gate array（FPGA）
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High Precision Absolute Gravity Meter Based on Time-to-Digital Conversion in FPGA 认领 引用 被引量：3
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作者 LIU Sanjun YANG Junhong CHEN Hao 《Wuhan University Journal of Natural Sciences》 CAS CSCD 2021年第4期358-364,共7页
This paper proposes a novel method to design a high precision portable gravity acceleration meter on the Field Programmable Gate Array(FPGA)platform.Two technologies are used in FPGA to improve the time measurement ac... This paper proposes a novel method to design a high precision portable gravity acceleration meter on the Field Programmable Gate Array(FPGA)platform.Two technologies are used in FPGA to improve the time measurement accuracy to 54 ps and the measurement accuracy of g to the level of 1μGal(1 Gal=1 cm/s2).The one is the proposed clock rising edge counting method for measuring the coarse time,in which the measured coarse time resolution can reach 5 ns by setting the clock frequency up to 200 MHz.The other is the realization of the time-to-digital conversion(TDC)circuits in FPGA which can further improve the time measurement accuracy to 54 ps.In the TDC circuit,we analyze the influence of the frequency stability of crystal oscillator and the distance of infrared tube on the measurement accuracy of g.The increase of frequency stability(10–9to 10–11)can greatly improve the measurement accuracy of g(5.8143 to 2.0799μGal),but further increase of frequency stability(10–11to 10–12)has little effect on improving the accuracy of g.Through analysis and simulation,it is found that the setting of distance between laser pair also has a great influence on the accuracy of g.Only when the distance is set to the optimal,we can make the accuracy of g the highest.In this paper,the method of obtaining the best distance and the corresponding accuracy of g are given.In addition,the proposed system uses Nios II soft core processor to implement all the controlling,calculation and display functions,which improves system integration,reduces system cost and meets the needs of field geological survey and gravity prospecting. 展开更多
关键词 Field Programmable Gate Array(FPGA) gravity acceleration meter time-to-digital conversion(TDC)
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