期刊文献+
任意字段
题名或关键词
题名
关键词
摘要
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息
共找到29篇文章
< 1 2 >
每页显示 20 50 100
已选0条
引用分析
参考文献
引证文献
 统计分析
检索结果
已选文献
显示方式：
Exponential sine chaotification model for enhancing chaos and its hardware implementation 认领 引用
1
作者 Rui Wang Meng-Yang Li Hai-Jun Luo 《Chinese Physics B》 SCIE EI CAS CSCD 2022年第8期337-346,共10页
Chaotic systems have been intensively studied for their roles in many applications, such as cryptography, secure communications, nonlinear controls, etc. However, the limited complexity of existing chaotic systems wea... Chaotic systems have been intensively studied for their roles in many applications, such as cryptography, secure communications, nonlinear controls, etc. However, the limited complexity of existing chaotic systems weakens chaos-based practical applications. Designing chaotic maps with high complexity is attractive. This paper proposes the exponential sine chaotification model(ESCM), a method of using the exponential sine function as a nonlinear transform model, to enhance the complexity of chaotic maps. To verify the performance of the ESCM, we firstly demonstrated it through theoretical analysis. Then, to exhibit the high efficiency and usability of ESCM, we applied ESCM to one-dimensional(1D) and multidimensional(MD) chaotic systems. The effects were examined by the Lyapunov exponent and it was found that enhanced chaotic maps have much more complicated dynamic behaviors compared to their originals. To validate the simplicity of ESCM in hardware implementation, we simulated three enhanced chaotic maps using a digital signal processor(DSP). To explore the ESCM in practical application, we applied ESCM to image encryption. The results verified that the ESCM can make previous chaos maps competitive for usage in image encryption. 展开更多
关键词 chaotic system nonlinear system image encryption hardware implementation
暂未订购 下载PDF
Features of hardware implementation of quasi-continuous observation devices with discrete receivers 认领 引用
2
作者 Oleksandr Maryliv Mykhailo Slonov 《Visual Computing for Industry,Biomedicine,and Art》 EI 2022年第1期71-77,共7页
This article proposes an approach to the formalization of tasks and conditions for the hardware implementation of quasi-continuous observation devices with discrete receivers in remote sensing systems.Observation devi... This article proposes an approach to the formalization of tasks and conditions for the hardware implementation of quasi-continuous observation devices with discrete receivers in remote sensing systems.Observation devices with a matrix are used in medicine,ecology,aerospace photography,and geodesy,among other fields.In the discrete receivers,the sampling of an image in the matrix receiver into pixels leads to a decrease in the spatial information of the object.In a greater extent,these disadvantages can be avoided by using photosensitive matrix with a regularly changing(controlled)density of elementary receivers-matrix(RCDOER-matrix).Currently,there is no substantiation of the tasks and conditions for the hardware implementation of RCDOER-matrix.The algorithmic formation of a quasi-continuous image of observation devices with the RCDOER-matrix is proposed.The algorithm used a formal pixel-by-pixel description of the signals in the image.This algorithm formalizes the requirements for creating a photosensitive RCDOER-matrix of a certain size,as well as for changing the mechanism for forming and saving a frame with observation results.The application of the developed method will allow multiplying the pixel size of the image relative to the pixel size of the RCDOER-matrix.Developed algorithms for RCDOER-matrix are supplemented by formalizing the tasks that arise when creating prototypes.In addition,the conditions for hardware implementation are proposed,which ensure the completeness of registration of the observation picture,and allow avoiding excessive pixel measurements.Thus,the results of the research carried out approximate the practical application of RCDOER-matrix. 展开更多
关键词 Discrete receivers Formalization of tasks Conditions of hardware implementation
暂未订购 下载PDF
A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard 认领 引用
3
作者 Yawen Wang Sini Bin +1 位作者 Shikai Zhu Xiaoting Hu 《Journal of Computer and Communications》 2024年第4期228-246,共19页
The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization... The SubBytes (S-box) transformation is the most crucial operation in the AES algorithm, significantly impacting the implementation performance of AES chips. To design a high-performance S-box, a segmented optimization implementation of the S-box is proposed based on the composite field inverse operation in this paper. This proposed S-box implementation is modeled using Verilog language and synthesized using Design Complier software under the premise of ensuring the correctness of the simulation result. The synthesis results show that, compared to several current S-box implementation schemes, the proposed implementation of the S-box significantly reduces the area overhead and critical path delay, then gets higher hardware efficiency. This provides strong support for realizing efficient and compact S-box ASIC designs. 展开更多
关键词 Advanced Encryption Standard (AES) S-Box Tower Field Hardware Implementation Application Specific Integration Circuit (ASIC)
暂未订购 下载PDF
Neurodynamic Optimization Approaches With Fixed-Time Convergence for Nash Equilibrium Seeking:Theory and Hardware Experiment 认领 引用
4
作者 Xingxing Ju Xinsong Yang +2 位作者 Chuandong Li Gang Feng Daniel W.C.Ho 《IEEE/CAA Journal of Automatica Sinica》 SCIE EI CSCD 2026年第3期704-714,共11页
The convergence rate is one of the key performance measures for Nash equilibrium(NE)seeking strategies.In this work,we present several novel fast decoupled/coupled time-varying neurodynamic optimization approaches wit... The convergence rate is one of the key performance measures for Nash equilibrium(NE)seeking strategies.In this work,we present several novel fast decoupled/coupled time-varying neurodynamic optimization approaches with fixed-time(FT)convergence to Nash equilibrium seeking in non-cooperative games.The dynamics trajectories are demonstrated to converge to the NE solution within a fixed time from any initial states.The proposed neurodynamic networks exhibit a faster convergence rate with appropriately selected time-varying coefficients.Additionally,the upper bounds of the convergence time of the proposed NE seeking networks are smaller than those for strategies with constant coefficients.The robustness of the proposed NE seeking neurodynamic approaches under bounded perturbations is further studied.The efficacy and practicality of the proposed NE seeking approaches are validated through simulations and field-programmable gate array(FPGA)experiments on duopoly market games. 展开更多
关键词 Fixed-time(FT)convergence hardware implementation Nash equilibrium(NE) neurodynamic optimization approaches
暂未订购 下载PDF
Optimizing AES S-Box Implementation:A SAT-Based Approach with Tower Field Representations 认领 引用
5
作者 Jingya Feng Ying Zhao +1 位作者 Tao Ye Wei Feng 《Computers, Materials & Continua》 SCIE EI 2025年第4期1515-1531,共17页
The efficient implementation of the Advanced Encryption Standard(AES)is crucial for network data security.This paper presents novel hardware implementations of the AES S-box,a core component,using tower field represen... The efficient implementation of the Advanced Encryption Standard(AES)is crucial for network data security.This paper presents novel hardware implementations of the AES S-box,a core component,using tower field representations and Boolean Satisfiability(SAT)solvers.Our research makes several significant contri-butions to the field.Firstly,we have optimized the GF(24)inversion,achieving a remarkable 31.35%area reduction(15.33 GE)compared to the best known implementations.Secondly,we have enhanced multiplication implementa-tions for transformation matrices using a SAT-method based on local solutions.This approach has yielded notable improvements,such as a 22.22%reduction in area(42.00 GE)for the top transformation matrix in GF((24)2)-type S-box implementation.Furthermore,we have proposed new implementations of GF(((22)2)2)-type and GF((24)2)-type S-boxes,with the GF(((22)2)2)-type demonstrating superior performance.This implementation offers two variants:a small area variant that sets new area records,and a fast variant that establishes new benchmarks in Area-Execution-Time(AET)and energy consumption.Our approach significantly improves upon existing S-box implementations,offering advancements in area,speed,and energy consumption.These optimizations contribute to more efficient and secure AES implementations,potentially enhancing various cryptographic applications in the field of network security. 展开更多
关键词 AES S-box SAT optimization tower field hardware implementation area efficiency energy consumption
暂未订购 下载PDF
Optimizing solar energy efficiency with an improved hill-climbing maximum power point tracking control approach: hardware implementation 认领 引用
6
作者 Yassine El Alami Elmostafa Chetouani +6 位作者 Hamza Mokhliss Fatima Ouerradi Mohssin Aoutoul Said Bounouar Rachid Bendaoud Ahmed Faize Redouane Rmaily 《Clean Energy》 EI CSCD 2024年第5期167-176,共10页
This article implements maximum power point tracking(MPPT)based on the improved hill-climbing algorithm for photovoltaic(PV)systems feeding resistive loads.A direct current-to-direct current boost converter is inserte... This article implements maximum power point tracking(MPPT)based on the improved hill-climbing algorithm for photovoltaic(PV)systems feeding resistive loads.A direct current-to-direct current boost converter is inserted between the PV system and the load to achieve matching.The converter is managed using MPPT based on the hill-climbing algorithm.The objective of this paper is to optimize the code program to achieve the best compromise between accuracy and rapidity by implementing this algorithm using a microcontroller.Two PV systems are tested under identical meteorological conditions.In the first,an improved hill-climbing MPPT controller is used whereas,in the second,the conventional version is employed.The experimental results obtained show a signifi-cant enhancement in terms of speed for the improved algorithm with a value of 0.4 s for the response time and 3%for the oscillation power;those values remain satisfactory in terms of precision of the algorithm compared with the conventional system studied and the compared algorithm from the literature. 展开更多
关键词 DC/DC boost converter hardware implementation improved hill climbing MPPT photovoltaic system
暂未订购 下载PDF
[0,1]Modulated Backscatter with Lower-Power Integration of Sensing and Communication for I-IoE in 6G 认领 引用
7
作者 Tao Jiang Miaoran Peng +2 位作者 Yu Zhang Xin Zhu Shuqi Tang 《Engineering》 SCIE EI CSCD 2026年第6期354-364,共11页
Artificial intelligence for the intelligent Internet of Everything(I-IoE)establishes a four-dimensional interconnection among people,data,processes,and things,providing possibilities for the next generation of industr... Artificial intelligence for the intelligent Internet of Everything(I-IoE)establishes a four-dimensional interconnection among people,data,processes,and things,providing possibilities for the next generation of industrial revolution.Against the ultra-high power consumption brought by massive connectivity,pas-sive backscatter communication has emerged as a promising paradigm for the I-IoE.However,even with a well-designed communication module,integrating sensing components significantly multiplies the overall system complexity and cost in the context of the{0,1}modulation paradigm.In this paper,we introduce a[0,1]modulated backscatter architecture that achieves the seamless integration of passive sensing and communication.Unlike the conventional backscatter of reading,encoding,and reflecting,the proposed[0,1]modulated backscatter directly converts environmental physical quantities into con-tinuous frequency-modulated square waves.Building on this concept,we propose an intelligent detec-tion method based on graph dimensionality reduction.This method achieves low computational complexity at the receiver by leveraging a pre-measured dataset.We then present a hardware commu-nication system that performs data collection,transmission,and demodulation,providing experimental validation for the proposed architecture.Furthermore,simulation results verify the feasibility of a contin-uous frequency division multiple-access method for large-scale tags.The experimental results demon-strate the superior performance of the proposed scheme.This work provides a potential breakthrough for achieving ultra-low-power integrated sensing and communication in sixth-generation wireless com-munication networks. 展开更多
关键词 Wireless communication Backscatter communication Sensing Artificial intelligence Hardware implementation
暂未订购 下载PDF
Spatially Reconfigurable Antenna Arrays for 6G Networks:Modeling,Methods,and Applications 认领 引用
8
作者 Wen Wang Yongming Huang Cheng Zhang 《Journal of Communications and Information Networks》 EI CSCD 2026年第2期170-202,共33页
Spatially reconfigurable antenna arrays(SRAAs)have recently emerged as a promising paradigm for enhancing wireless system performance by treating antenna position and orientation as new spatial degrees of freedom(DoFs... Spatially reconfigurable antenna arrays(SRAAs)have recently emerged as a promising paradigm for enhancing wireless system performance by treating antenna position and orientation as new spatial degrees of freedom(DoFs).Unlike conventional fixed-geometry antenna arrays,SRAAs enable geometry-aware adaptation of the physical aperture,thereby allowing wireless systems to actively exploit spatial channel variations beyond signal-domain processing.This capability is particularly attractive for future sixth-generation(6G)networks that operate in highly dynamic propagation environments and face stringent performance requirements.This review provides a comprehensive and system-oriented overview of SRAAs from both theoretical and practical perspectives.Firstly,we present a unified and geometry-aware channel modeling framework for spatial reconfiguration at different architectural granularities.Secondly,we analyze how position-and orientation-induced channel variations,along with their combined effects,and enable performance gains without relying solely on massive antenna scaling.Afterwards,we survey design and optimization methods for position-orientation reconfiguration,covering both model-and learning-based techniques.Practical considerations are also discussed through a systematic review of hardware implementation options and channel estimation techniques under spatial reconfiguration.To further illustrate the system-level ben-efits of SRAAs,representative applications are examined,including point-to-point and multiuser multiple-input multiple-output(MIMO),cell-free massive MIMO,as well as aerial and mobile communications.A dedicated case study on six-dimensional aerial rotatable antenna(6DARA)-enabled cell-free networks is provided to demonstrate how array-wise position and orientation control,combined with distributed optimization,can achieve substantial performance gains with manageable complexity.Finally,we outline key issues and future directions for the large-scale and practical deployment of SRAAs in 6G wireless networks. 展开更多
关键词 spatially reconfigurable antenna arrays spatial degrees of freedom movable and rotatable antennas multiple-input multiple-output channel modeling and estimation optimization methods hardware implementation sixth-generation networks
Two Bit-Serial Architectures for Check Node Update in Min-Sum Decoding of LDPC Codes 认领 引用
9
作者 Hu Qing He Xuan +2 位作者 Luo Lisha Cai Kui Tang Xiaohu 《China Communications》 SCIE EI CSCD 2026年第3期142-150,共9页
Implementing check node(CN)update based on the minimum value(MV)and second MV of incoming message magnitudes is crucial for Min-Sum Algorithms(MSAs).In the category of bit-serial implementations,existing schemes suffe... Implementing check node(CN)update based on the minimum value(MV)and second MV of incoming message magnitudes is crucial for Min-Sum Algorithms(MSAs).In the category of bit-serial implementations,existing schemes suffer from decoding performance degradation,large hardware areas,and/or long latency.In this paper,we propose two efficient CN update functions based on the MV and an approximate second MV,and design bit-serial architectures to implement them.Simulation results show that our functions exhibit the minimum decoding performance degradation compared to the existing functions using approximate second MVs.Moreover,the applicationspecific integrated circuits(ASIC)implementation results demonstrate the advantages of our architectures in terms of area,latency,etc. 展开更多
关键词 bit-serial check node update hardware implementation LDPC code min-sum algorithm
暂未订购 下载PDF
List-Serial Pipelined Hardware Architecture for SCL Decoding of Polar Codes 认领 引用 被引量：4
10
作者 Zhongxiu Feng Cong Niu +3 位作者 Zhengyu Zhang Jiaxi Zhou Daiming Qu Tao Jiang 《China Communications》 SCIE CSCD 2023年第3期175-184,共10页
For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from h... For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously,which are unfriendly to the devices with limited logical resources,such as field programmable gate arrays(FPGAs).In this paper,we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding,where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency.Moreover,we employ only one successive cancellation(SC)decoder core without L×L crossbars,and reduce the number of inputs of the metric sorter from 2L to L+2.Finally,the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss. 展开更多
关键词 successive cancellation list decoding po-lar codes hardware implementation pipelined archi-tecture
暂未订购 下载PDF
Implementation of an 8-bit bit-slice AES S-box with rapid single flux quantum circuits 认领 引用 被引量：1
11
作者 Ruo-Ting Yang Xin-Yi Xue +4 位作者 Shu-Cheng Yang Xiao-Ping Gao Jie Ren Wei Yan Zhen Wang 《Chinese Physics B》 SCIE EI CAS CSCD 2022年第9期604-610,共7页
Rapid single flux quantum(RSFQ)circuits are a kind of superconducting digital circuits,having properties of a natural gate-level pipelining synchronous sequential circuit,which demonstrates high energy efficiency and ... Rapid single flux quantum(RSFQ)circuits are a kind of superconducting digital circuits,having properties of a natural gate-level pipelining synchronous sequential circuit,which demonstrates high energy efficiency and high throughput advantage.We find that the high-throughput and high-speed performance of RSFQ circuits can take the advantage of a hardware implementation of the encryption algorithm,whereas these are rarely applied to this field.Among the available encryption algorithms,the advanced encryption standard(AES)algorithm is an advanced encryption standard algorithm.It is currently the most widely used symmetric cryptography algorithm.In this work,we aim to demonstrate the SubByte operation of an AES-128 algorithm using RSFQ circuits based on the SIMIT Nb03 process.We design an AES S-box circuit in the RSFQ logic,and compare its operational frequency,power dissipation,and throughput with those of the CMOS-based circuit post-simulated in the same structure.The complete RSFQ S-box circuit costs a total of 42237 Josephson junctions with nearly 130 Gbps throughput under the maximum simulated frequency of 16.28 GHz.Our analysis shows that the frequency and throughput of the RSFQ-based S-box are about four times higher than those of the CMOS-based S-box.Further,we design and fabricate a few typical modules of the S-box.Subsequent measurements demonstrate the correct functioning of the modules in both low and high frequencies up to 28.8 GHz. 展开更多
关键词 RSFQ AES S-box hardware implementation
暂未订购 下载PDF
Low-Complexity Stochastic Belief Propagation Detector for Large-Scale MIMO Systems 认领 引用
12
作者 Li Muhao Yang Junmei +2 位作者 Chen Jienan Tan Xiaosi Zhang Chuan 《China Communications》 SCIE EI CSCD 2026年第5期168-184,共17页
For large-scale multiple-input multipleoutput(MIMO)systems,iterative detection algorithms based on belief propagation(BP)have shown nearoptimal performance.However,the existing deterministic implementations of BP dete... For large-scale multiple-input multipleoutput(MIMO)systems,iterative detection algorithms based on belief propagation(BP)have shown nearoptimal performance.However,the existing deterministic implementations of BP detection are considerably complex,particularly for MIMO systems with a large scale.This paper proposes an alternative approach using stochastic computation.This paper introduces a hardware architecture for stochastic message updating of observation nodes and symbol nodes.The signed stochastic real division(SRD)and the stochastic real addition(SRA)are proposed for latency consideration,and multi-bit designs are proposed to improve the performance and reduce the stream length.The look up table(LUT)has been modified for serial input to enhance hardware efficiency.Simulation results demonstrate that for large-scale MIMO systems with either QPSK or 16-QAM,the stochastic BP detector achieves similar performance as the deterministic one.To highlight its implementation advantage,an 8×32 stochastic MIMO detector with QPSK is implemented.Results show that its hardware efficiency is about 10 times greater than existing works and has lower complexity compared with deterministic designs. 展开更多
关键词 belief propagation(BP) hardware implementation large-scale MIMO stochastic computation
暂未订购 下载PDF
High-performance hardware architecture of elliptic curve cryptography processor over GF(2163) 认领 引用
13
作者 Yong-ping DAN Xue-cheng ZOU +2 位作者 Zheng-lin LIU Yu HAN Li-hua YI 《Journal of Zhejiang University-SCIENCE A》 SCIE EI CAS 2009年第2期301-310,共10页
We propose a novel high-performance hardware architecture of processor for elliptic curve scalar multiplication based on the Lopez-Dahab algorithm over GF（2^163） in polynomial basis representation. The processor can... We propose a novel high-performance hardware architecture of processor for elliptic curve scalar multiplication based on the Lopez-Dahab algorithm over GF（2^163） in polynomial basis representation. The processor can do all the operations using an efficient modular arithmetic logic unit, which includes an addition unit, a square and a carefully designed multiplication unit. In the proposed architecture, multiplication, addition, and square can be performed in parallel by the decomposition of computation. The point addition and point doubling iteration operations can be performed in six multiplications by optimization and solution of data dependency. The implementation results based on Xilinx VirtexⅡ XC2V6000 FPGA show that the proposed design can do random elliptic curve scalar multiplication GF（2^163） in 34.11 μs, occupying 2821 registers and 13 376 LUTs. 展开更多
关键词 Elliptic curve cryptography （ECC） Scalar multiplication Hardware implementation
暂未订购 下载PDF
Two Methods of AES Implementation Based on CPLD/FPGA 认领 引用
14
作者 刘常澍 彭艮鹏 王晓卓 《Transactions of Tianjin University》 EI CAS 2004年第4期285-290,共6页
This paper describes two single-chip——complex programmable logic devices/field programmable gate arrays(CPLD/FPGA)——implementations of the new advanced encryption standard (AES) algorithm based on the basic iterat... This paper describes two single-chip——complex programmable logic devices/field programmable gate arrays(CPLD/FPGA)——implementations of the new advanced encryption standard (AES) algorithm based on the basic iteration architecture (design [A]) and the hybrid pipelining architecture (design [B]). Design [A] is an encryption-and-decryption implementation based on the basic iteration architecture. This design not only supports 128-bit, 192-bit, 256-bit keys, but saves hardware resources because of the iteration architecture and sharing technology. Design [B] is a method of the 2×2 hybrid pipelining architecture. Based on the AES interleaved mode of operation, the design successfully accomplishes the algorithm, which operates in the feedback mode (cipher block chaining). It not only guarantees security of encryption/decryption, but obtains high data throughput of 1.05 Gb/s. The two designs have been realized on Aitera′s EP20k300EBC652-1 devices. 展开更多
关键词 advanced encryption standard (AES) encryption decryption feedback mode hybrid pipelining hardware implementation
暂未订购 下载PDF
A Quality of Service Analysis of FPGA-Accelerated Conv2D Architectures for Brain Tumor Multi-Classification 认领 引用
15
作者 Ayoub Mhaouch Wafa Gtifa +2 位作者 Turke Althobaiti Hamzah Faraj Mohsen Machhout 《Computers, Materials & Continua》 SCIE EI 2025年第9期5637-5663,共27页
In medical imaging,accurate brain tumor classification in medical imaging requires real-time processing and efficient computation,making hardware acceleration essential.Field Programmable Gate Arrays(FPGAs)offer paral... In medical imaging,accurate brain tumor classification in medical imaging requires real-time processing and efficient computation,making hardware acceleration essential.Field Programmable Gate Arrays(FPGAs)offer parallelism and reconfigurability,making them well-suited for such tasks.In this study,we propose a hardware-accelerated Convolutional Neural Network(CNN)for brain cancer classification,implemented on the PYNQ-Z2 FPGA.Our approach optimizes the first Conv2D layer using different numerical representations:8-bit fixed-point(INT8),16-bit fixed-point(FP16),and 32-bit fixed-point(FP32),while the remaining layers run on an ARM Cortex-A9 processor.Experimental results demonstrate that FPGA acceleration significantly outperforms the CPU(Central Processing Unit)based approach.The obtained results emphasize the critical importance of selecting the appropriate numerical representation for hardware acceleration in medical imaging.On the PYNQ-Z2 FPGA,the INT8 achieves a 16.8%reduction in latency and 22.2%power savings compared to FP32,making it ideal for real-time and energy-constrained applications.FP16 offers a strong balance,delivering only a 0.1%drop in accuracy compared to FP32(94.1%vs.94.2%)while improving latency by 5%and reducing power consumption by 11.1%.Compared to prior works,the proposed FPGA-based CNN model achieves the highest classification accuracy(94.2%)with a throughput of up to 1.562 FPS,outperforming GPU-based and traditional CPU methods in both accuracy and hardware efficiency.These findings demonstrate the effectiveness of FPGA-based AI acceleration for real-time,power-efficient,and high-performance brain tumor classification,showcasing its practical potential in next-generation medical imaging systems. 展开更多
关键词 Brain cancer hardware implementation convolutional neural networks performance evaluation efficient computing real-time medical applications
暂未订购 下载PDF
Memristors-coupled neuron models with multiple firing patterns and homogeneous and heterogeneous multistability 认领 引用
16
作者 Xuan Wang Santo Banerjee +1 位作者 Yinghong Cao Jun Mou 《Chinese Physics B》 SCIE EI CAS CSCD 2024年第10期176-189,共14页
Memristors are extensively used to estimate the external electromagnetic stimulation and synapses for neurons.In this paper,two distinct scenarios,i.e.,an ideal memristor serves as external electromagnetic stimulation... Memristors are extensively used to estimate the external electromagnetic stimulation and synapses for neurons.In this paper,two distinct scenarios,i.e.,an ideal memristor serves as external electromagnetic stimulation and a locally active memristor serves as a synapse,are formulated to investigate the impact of a memristor on a two-dimensional Hindmarsh-Rose neuron model.Numerical simulations show that the neuronal models in different scenarios have multiple burst firing patterns.The introduction of the memristor makes the neuronal model exhibit complex dynamical behaviors.Finally,the simulation circuit and DSP hardware implementation results validate the physical mechanism,as well as the reliability of the biological neuron model. 展开更多
关键词 memristor multistability Hamilton energy firing pattern Neuron model hardware implementation
暂未订购 下载PDF
Create Your Own Data and Energy Integrated Communication Network:A Brief Tutorial and a Prototype System 认领 引用 被引量：4
17
作者 Yali Zheng Yitian Zhang +2 位作者 Yang Wang Jie Hu Kun Yang 《China Communications》 SCIE CSCD 2020年第9期193-209,共17页
In order to satisfy the ever-increasing energy appetite of the massive battery-powered and batteryless communication devices,radio frequency(RF)signals have been relied upon for transferring wireless power to them.The... In order to satisfy the ever-increasing energy appetite of the massive battery-powered and batteryless communication devices,radio frequency(RF)signals have been relied upon for transferring wireless power to them.The joint coordination of wireless power transfer(WPT)and wireless information transfer(WIT)yields simultaneous wireless information and power transfer(SWIPT)as well as data and energy integrated communication network(DEIN).However,as a promising technique,few efforts are invested in the hardware implementation of DEIN.In order to make DEIN a reality,this paper focuses on hardware implementation of a DEIN.It firstly provides a brief tutorial on SWIPT,while summarising the latest hardware design of WPT transceiver and the existing commercial solutions.Then,a prototype design in DEIN with full protocol stack is elaborated,followed by its performance evaluation. 展开更多
关键词 data and energy integrated communication network(DEIN) wireless power transfer(WPT) simultaneously wireless information and power transfer(SWIPT) RF charging hardware implementation
暂未订购 下载PDF
A Novel Masking Scheme for SM3 Based MAC 认领 引用 被引量：2
18
作者 QU Kaige WU Liji +2 位作者 WANG An REN Yanting ZHANG Xiangmin 《China Communications》 SCIE CSCD 2015年第6期11-21,共11页
The Chinese hash algorithm SM3 is verified to be secure enough,but improper hardware implementation may lead to leakage.A masking scheme for SM3 algorithm is proposed to ensure the security of SM3 based Message Authen... The Chinese hash algorithm SM3 is verified to be secure enough,but improper hardware implementation may lead to leakage.A masking scheme for SM3 algorithm is proposed to ensure the security of SM3 based Message Authentication Code(MAC).Our scheme was implemented in hardware,which utilizes hardware oriented secure conversion techniques between boolean and arithmetic masking.Security evaluation based on SAKURA-G FPGA board has been done with 2000 power traces from 2000 random plaintexts with random plaintext masks and random key masks.It has been verified that the masked SM3 hardware implementation shows no intermediate value leakage as expected.Our masked SM3 hardware can resist first-order correlation power attack(CPA) and collision correlation attack. 展开更多
关键词 SM3 algorithm masking scheme hardware implementation power analysis boolean and arithmetic masking conversion
暂未订购 下载PDF
An Efficient AES 32-Bit Architecture Resistant to Fault Attacks 认领 引用 被引量：2
19
作者 Hassen Mestiri Imen Barraj +1 位作者 Abdullah Alsir Mohamed Mohsen Machhout 《Computers, Materials & Continua》 SCIE EI 2022年第2期3667-3683,共17页
The Advanced Encryption Standard cryptographic algorithm,named AES,is implemented in cryptographic circuits to ensure high security level to any system which required confidentiality and secure information exchange.On... The Advanced Encryption Standard cryptographic algorithm,named AES,is implemented in cryptographic circuits to ensure high security level to any system which required confidentiality and secure information exchange.One of the most effective physical attacks against the hardware implementation of AES is fault attacks which can extract secret data.Until now,a several AES fault detection schemes against fault injection attacks have been proposed.In this paper,so as to ensure a high level of security against fault injection attacks,a new efficient fault detection scheme based on the AES architecture modification has been proposed.For this reason,the AES 32-bit round is divided into two half rounds and input and pipeline registers are implemented between them.The proposed scheme is independent of the procedure the AES is implemented.Thus,it can be implemented to secure the pipeline and iterative architectures.To evaluate the robustness of the proposed fault detection scheme against fault injection attacks,we conduct a transient and permanent fault attacks and then we determine the fault detection capability;it is about 99.88585%and 99.9069%for transient and permanent faults respectively.We have modeled the AES fault detection scheme using VHDL hardware language and through hardware FPGA implementation.The FPGA results demonstrate that our scheme can efficiently protect the AES hardware implementation against fault attacks.It can be simply implemented with low complexity.In addition,the FPGA implementation performances prove the low area overhead and the high efficiency and working frequency for the proposed AES detection scheme. 展开更多
关键词 Security cryptographic circuits AES hardware implementation fault detection fault attacks
暂未订购 下载PDF
An optimized run-length based algorithm for sparse remote sensing image labeling 认领 引用 被引量：1
20
作者 Shen-shen Luan Bo-wen Cheng +3 位作者 Shuai Jiang Yu-hang Wu Zong-ling Li Ji-yang Yu 《Defence Technology（防务技术）》 SCIE EI CAS CSCD 2022年第4期663-677,共15页
Labeling of the connected components is the key operation of the target recognition and segmentation in remote sensing images.The conventional connected-component labeling(CCL) algorithms for ordinary optical images a... Labeling of the connected components is the key operation of the target recognition and segmentation in remote sensing images.The conventional connected-component labeling(CCL) algorithms for ordinary optical images are considered time-consuming in processing the remote sensing images because of the larger size.A dynamic run-length based CCL algorithm(Dy RLC) is proposed in this paper for the large size,big granularity sparse remote sensing image,such as space debris images and ship images.In addition,the equivalence matrix method is proposed to help design the pre-processing method to accelerate the equivalence labels resolving.The result shows our algorithm outperforms 22.86% on execution time than the other algorithms in space debris image dataset.The proposed algorithm also can be implemented on the field programming logical array(FPGA) to enable the realization of the real-time processing on-board. 展开更多
关键词 Connected-component labeling Label equivalence resolving Hardware implementation Equivalence matrix On-board processing
暂未订购 下载PDF
已选0条
引用分析
参考文献
引证文献
 统计分析
检索结果
已选文献
上一页 1 2 下一页 到第 页
在线咨询 使用帮助 返回顶部 意见反馈