The efficient implementation of the Advanced Encryption Standard(AES)is crucial for network data security.This paper presents novel hardware implementations of the AES S-box,a core component,using tower field represen...The efficient implementation of the Advanced Encryption Standard(AES)is crucial for network data security.This paper presents novel hardware implementations of the AES S-box,a core component,using tower field representations and Boolean Satisfiability(SAT)solvers.Our research makes several significant contri-butions to the field.Firstly,we have optimized the GF(24)inversion,achieving a remarkable 31.35%area reduction(15.33 GE)compared to the best known implementations.Secondly,we have enhanced multiplication implementa-tions for transformation matrices using a SAT-method based on local solutions.This approach has yielded notable improvements,such as a 22.22%reduction in area(42.00 GE)for the top transformation matrix in GF((24)2)-type S-box implementation.Furthermore,we have proposed new implementations of GF(((22)2)2)-type and GF((24)2)-type S-boxes,with the GF(((22)2)2)-type demonstrating superior performance.This implementation offers two variants:a small area variant that sets new area records,and a fast variant that establishes new benchmarks in Area-Execution-Time(AET)and energy consumption.Our approach significantly improves upon existing S-box implementations,offering advancements in area,speed,and energy consumption.These optimizations contribute to more efficient and secure AES implementations,potentially enhancing various cryptographic applications in the field of network security.展开更多
Single or multiple S-boxes are widely used in image encryption schemes, and in many image encryption schemes the asynchronous encryption structure is utilized, which separates the processes of substitution and diffusi...Single or multiple S-boxes are widely used in image encryption schemes, and in many image encryption schemes the asynchronous encryption structure is utilized, which separates the processes of substitution and diffusion. In this paper, we analyze the defects of this structure based on the example of an article and crack it using a simpler method. To address the defects of the asynchronous encryption structure, a novel encryption scheme is proposed, in which the structure of synchronous substitution and diffusion based on double S-boxes is utilized, so the processes of substitution and diffusion are combined together and the attackers cannot crack the cryptosystem by any of the processes. The simulation results and security analysis show that the proposed encryption scheme is safer and more efficient to expediently use in the real-time system.展开更多
S-boxes can be the core component of block ciphers,and how to efficiently generate S-boxes with strong cryptographic properties appears to be an important task in the design of block ciphers.In this work,an optimized ...S-boxes can be the core component of block ciphers,and how to efficiently generate S-boxes with strong cryptographic properties appears to be an important task in the design of block ciphers.In this work,an optimized model based on the generative adversarial network(GAN)is proposed to generate 8-bit S-boxes.The central idea of this optimized model is to use loss function constraints for GAN.More specially,the Advanced Encryption Standard(AES)S-box is used to construct the sample dataset via the affine equivalence property.Then,three models are respectively built and cross-trained to generate 8-bit S-boxes based on three extended frameworks of GAN,i.e.,Deep Convolution Generative Adversarial Networks(DCGAN),Wasserstein Generative Adversarial Networks(WGAN),and WassersteinGenerativeAdversarial NetworkwithGradient Penalty(WGANGP).Besides,an optimized model based onWGAN-GP referred to asWGPIM is also proposed,which adds the loss function constraints to the generator network of the WGAN-GP model,including bijection loss,differential uniformity loss,and nonlinearity loss.In this case,8-bit S-boxes can be generated with cross-training.Experimental results illustrate that the WGP-IM model can generate S-boxes with excellent cryptographic properties.In particular,the optimal differential uniformity of the generated S-boxes can be reduced to 8,and the nonlinearity can be up to 104.Compared with previous S-box generation methods,this new method is simpler and it can generate S-boxes with excellent cryptographic properties.展开更多
The algorithm is an image encryption algorithm based on the improved baker transformation and chaotic substitution box(S-box). It mainly uses the initial values and parameters of a one-dimensional logistic chaotic sys...The algorithm is an image encryption algorithm based on the improved baker transformation and chaotic substitution box(S-box). It mainly uses the initial values and parameters of a one-dimensional logistic chaotic system as an encryption key. Specifically, in the image scrambling stage, the algorithm primarily uses an improved baker transform method to process the image. In the image diffusion stage, the algorithm first uses the chaotic S-box method to process the encryption key. Secondly, an exclusive OR(XOR) operation is performed on the image and the encryption key to initially diffuse the image. Finally, the image is again diffused using the method of ortho XOR. Simulation analysis shows that the algorithm can achieve good encryption effect, simple and easy implementation, and good security. In the digital image communication transmission, it has good practical value.展开更多
Using composite field arithmetic in Galois field can result in the compact Rijndael S-Box. However, the power con- sumption of this solution is too large to be used in resource-limited embedded systems. A full-custom ...Using composite field arithmetic in Galois field can result in the compact Rijndael S-Box. However, the power con- sumption of this solution is too large to be used in resource-limited embedded systems. A full-custom hardware implementation of composite field S-Box is proposed for these targeted domains in this paper. The minimization of power consumption is implemented by optimizing the architecture of the composite field S-Box and using the pass transmission gate (PTG) to realize the logic functions of S-Box. Power simulations were performed using the netlist extracted from the layout. HSPICE simulation results indicated that the proposed S-Box achieves low power consumption of about 130 μW at 10 MHz using 0.25 μm/2.5 V technology, while the consumptions of the positive polarity reed-muller (PPRM) based S-Box and composite field S-Box based on the conventional CMOS logic style are about 240 μW and 420 μW, respectively. The simulations also showed that the presented S-Box obtains better low-voltage operating property, which is clearly relevant for applications like sensor nodes, smart cards and radio frequency identification (RFID) tags.展开更多
Rapid single flux quantum(RSFQ)circuits are a kind of superconducting digital circuits,having properties of a natural gate-level pipelining synchronous sequential circuit,which demonstrates high energy efficiency and ...Rapid single flux quantum(RSFQ)circuits are a kind of superconducting digital circuits,having properties of a natural gate-level pipelining synchronous sequential circuit,which demonstrates high energy efficiency and high throughput advantage.We find that the high-throughput and high-speed performance of RSFQ circuits can take the advantage of a hardware implementation of the encryption algorithm,whereas these are rarely applied to this field.Among the available encryption algorithms,the advanced encryption standard(AES)algorithm is an advanced encryption standard algorithm.It is currently the most widely used symmetric cryptography algorithm.In this work,we aim to demonstrate the SubByte operation of an AES-128 algorithm using RSFQ circuits based on the SIMIT Nb03 process.We design an AES S-box circuit in the RSFQ logic,and compare its operational frequency,power dissipation,and throughput with those of the CMOS-based circuit post-simulated in the same structure.The complete RSFQ S-box circuit costs a total of 42237 Josephson junctions with nearly 130 Gbps throughput under the maximum simulated frequency of 16.28 GHz.Our analysis shows that the frequency and throughput of the RSFQ-based S-box are about four times higher than those of the CMOS-based S-box.Further,we design and fabricate a few typical modules of the S-box.Subsequent measurements demonstrate the correct functioning of the modules in both low and high frequencies up to 28.8 GHz.展开更多
Securing digital image data is a key concern in today’s information-driven society.Effective encryption techniques are required to protect sensitive image data,with the Substitution-box(S-box)often playing a pivotal ...Securing digital image data is a key concern in today’s information-driven society.Effective encryption techniques are required to protect sensitive image data,with the Substitution-box(S-box)often playing a pivotal role in many symmetric encryption systems.This study introduces an innovative approach to creating S-boxes for encryption algorithms.The proposed S-boxes are tested for validity and non-linearity by incorporating them into an image encryption scheme.The nonlinearity measure of the proposed S-boxes is 112.These qualities significantly enhance its resistance to common cryptographic attacks,ensuring high image data security.Furthermore,to assess the robustness of the S-boxes,an encryption system has also been proposed and the proposed S-boxes have been integrated into the designed encryption system.To validate the effectiveness of the proposed encryption system,a comprehensive security analysis including brute force attack and histogram analysis has been performed.In addition,to determine the level of security during the transmission and storage of digital content,the encryption system’s Number of Pixel Change Rate(NPCR),and Unified Averaged Changed Intensity(UACI)are calculated.The results indicate a 99.71%NPCR and 33.51%UACI.These results demonstrate that the proposed S-boxes offer a significant level of security for digital content throughout its transmission and storage.展开更多
A substitution box (S-box) plays an important role in cryptographic algorithms.The design of S-box using chaotic systems has attracted a great deal of attention in recent years.A new method for obtaining cryptographic...A substitution box (S-box) plays an important role in cryptographic algorithms.The design of S-box using chaotic systems has attracted a great deal of attention in recent years.A new method for obtaining cryptographically strong S-boxes based on spatiotemporal chaotic system is proposed in this paper.The discretized Baker map and affine transformation are used orderly by an algorithm to shuffle the table generated by the spatiotemporal chaotic system.The cryptographical properties of these S-boxes such as bijection,nonlinearity,strict avalanche,output bits independence and equiprobable input /output XOR distribution are analyzed.The results of numerical analysis show that the S-box designed by this method can against several attacks and all the criteria for designing good S-box can be satisfied approximately.More strong S-boxes can be obtained by this method with the change of the original conditions or control parameters of the spatiotemporal chaos system.Furthermore,our approach is suitable for practical application in designing cryptosystem.展开更多
Multi-objective genetic algorithm is much suitable for solving multi-objective optimization problems. By use of Genetic algorithm, the optimization of S-boxes is explored in this paper. Results of the experiments show...Multi-objective genetic algorithm is much suitable for solving multi-objective optimization problems. By use of Genetic algorithm, the optimization of S-boxes is explored in this paper. Results of the experiments show that, with heuristic mutation strategy, the algorithm has high searching efficiency and fast convergence speed. Meanwhile, we also have take the avalanche probability of S-boxes into account, besides nonlinearity and difference uniformity. Under this method, an effective genetic algorithm for 6×6 S-boxes is provided and a number of S-boxes with good cryptographic capability can be obtained.展开更多
A side-channel attack(SCA)-resistant AES S-box implementation is proposed,which is an improvement from the power-aware hiding(PAH)S-box but with higher security and a smaller area.We use the composite field approach a...A side-channel attack(SCA)-resistant AES S-box implementation is proposed,which is an improvement from the power-aware hiding(PAH)S-box but with higher security and a smaller area.We use the composite field approach and apply the PAH method to the inversion in the nonlinear kernel and a masking method to the other parts.In addition,a delaymatched enable control technique is used to suppress glitches in the masked parts.The evaluation results show that its area is contracted to 63.3%of the full PAH S-box,and its power-delay product is much lower than that of the masking implementation.The leakage assessment using simulation power traces concludes that it has no detectable leakage under t-test and that it at least can thwart the moment-correlation analysis using 665000 noiseless traces.展开更多
To obtain a low-power and compact implementation of the advanced encryption standard (AES) S- box, an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper. In the presented S...To obtain a low-power and compact implementation of the advanced encryption standard (AES) S- box, an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper. In the presented S-box, some improvements were made as follows. (1) Level-sensitive latches were inserted in data path to block the propagation Of the dynamic hazards, which lowered the power of data path circuit. (2) Operations of latches were controlled by latch controllers based on presented asynchronous sequence element: LC-element, which utilized static asymmetric C-element to construct a simple and power-efficient circuit structure. (3) Implementation of the data path circuit was a semi-custom standard-cell circuit on 0.25μm complementary mental oxide semiconductor (CMOS) process; and the full-custom design methodology was adopted in the handshake circuit design. Experimental results show that the resulting circuit achieves nearly 46% improvement with moderate area penalty ( 11.7% ) compared with the related composite field S-box in power performance. The presented S-box circuit can be a hardware intelli-gent property (IP) embedded in the targeted systems such as wireless sensor networks (WSN), smart-cards and radio frequency identification (RFID).展开更多
Substitution boxes (S-Boxes) in advanced encryption standard (AES) are vulnerable to attacks bypower analysis.The general S-Boxes masking schemes in circuit level need to adjust the design flow andlibrary databases.Th...Substitution boxes (S-Boxes) in advanced encryption standard (AES) are vulnerable to attacks bypower analysis.The general S-Boxes masking schemes in circuit level need to adjust the design flow andlibrary databases.The masking strategies in algorithm level view each S-Box as an independent moduleand mask them respectively,which are costly in size and power for non-linear characteristic of S-Boxes.The new method uses dynamic inhomogeneous S-Boxes instead of traditional homogeneous S-Boxes,andarranges the S-Boxes randomly.So the power and data path delay of substitution unit become unpre-dictable.The experimental results demonstrate that this scheme takes advantages of the circuit character-istics of various S-Box implementations to eliminate the correlation between crypto operation and power.Itneeds less extra circuits and suits resource constrained applications.展开更多
基金supported in part by the National Natural Science Foundation of China(No.62162016)in part by the Innovation Project of Guangxi Graduate Education(Nos.YCBZ2023132 and YCSW2023304).
摘要The efficient implementation of the Advanced Encryption Standard(AES)is crucial for network data security.This paper presents novel hardware implementations of the AES S-box,a core component,using tower field representations and Boolean Satisfiability(SAT)solvers.Our research makes several significant contri-butions to the field.Firstly,we have optimized the GF(24)inversion,achieving a remarkable 31.35%area reduction(15.33 GE)compared to the best known implementations.Secondly,we have enhanced multiplication implementa-tions for transformation matrices using a SAT-method based on local solutions.This approach has yielded notable improvements,such as a 22.22%reduction in area(42.00 GE)for the top transformation matrix in GF((24)2)-type S-box implementation.Furthermore,we have proposed new implementations of GF(((22)2)2)-type and GF((24)2)-type S-boxes,with the GF(((22)2)2)-type demonstrating superior performance.This implementation offers two variants:a small area variant that sets new area records,and a fast variant that establishes new benchmarks in Area-Execution-Time(AET)and energy consumption.Our approach significantly improves upon existing S-box implementations,offering advancements in area,speed,and energy consumption.These optimizations contribute to more efficient and secure AES implementations,potentially enhancing various cryptographic applications in the field of network security.
基金Project supported by the Natural Science Foundation of Shaanxi Province,China(Grant No.2014JM8322)
摘要Single or multiple S-boxes are widely used in image encryption schemes, and in many image encryption schemes the asynchronous encryption structure is utilized, which separates the processes of substitution and diffusion. In this paper, we analyze the defects of this structure based on the example of an article and crack it using a simpler method. To address the defects of the asynchronous encryption structure, a novel encryption scheme is proposed, in which the structure of synchronous substitution and diffusion based on double S-boxes is utilized, so the processes of substitution and diffusion are combined together and the attackers cannot crack the cryptosystem by any of the processes. The simulation results and security analysis show that the proposed encryption scheme is safer and more efficient to expediently use in the real-time system.
基金supported in part by the National Natural Science Foundation of China(62062026,62272451)the Innovation Research Team Project of Guangxi in China(2019GXNSFGA245004)+1 种基金the Key Research and Development Program of Guangxi in China(2022AB05044)the Scientific Research Project of Young Innovative Talents of Guangxi(guike AD20238082).
摘要S-boxes can be the core component of block ciphers,and how to efficiently generate S-boxes with strong cryptographic properties appears to be an important task in the design of block ciphers.In this work,an optimized model based on the generative adversarial network(GAN)is proposed to generate 8-bit S-boxes.The central idea of this optimized model is to use loss function constraints for GAN.More specially,the Advanced Encryption Standard(AES)S-box is used to construct the sample dataset via the affine equivalence property.Then,three models are respectively built and cross-trained to generate 8-bit S-boxes based on three extended frameworks of GAN,i.e.,Deep Convolution Generative Adversarial Networks(DCGAN),Wasserstein Generative Adversarial Networks(WGAN),and WassersteinGenerativeAdversarial NetworkwithGradient Penalty(WGANGP).Besides,an optimized model based onWGAN-GP referred to asWGPIM is also proposed,which adds the loss function constraints to the generator network of the WGAN-GP model,including bijection loss,differential uniformity loss,and nonlinearity loss.In this case,8-bit S-boxes can be generated with cross-training.Experimental results illustrate that the WGP-IM model can generate S-boxes with excellent cryptographic properties.In particular,the optimal differential uniformity of the generated S-boxes can be reduced to 8,and the nonlinearity can be up to 104.Compared with previous S-box generation methods,this new method is simpler and it can generate S-boxes with excellent cryptographic properties.
基金supported by the National Natural Science Foundation of China (Grant No. 61672124)the Password Theory Project of the 13th Five-Year Plan National Cryptography Development Fund,China (Grant No. MMJJ20170203)+3 种基金the Liaoning Provincial Science and Technology Innovation Leading Talents Program Project,China (Grant No. XLYC1802013)the Key Research and Development Projects of Liaoning Province,China (Grant No. 2019020105-JH2/103)the Jinan City ‘20 universities’ Funding Projects Introducing Innovation Team Program,China (Grant No. 2019GXRC031)the “Double First-rate”Construction Project (“Innovation Project”),China (Grant No. SSCXXM013)。
摘要The algorithm is an image encryption algorithm based on the improved baker transformation and chaotic substitution box(S-box). It mainly uses the initial values and parameters of a one-dimensional logistic chaotic system as an encryption key. Specifically, in the image scrambling stage, the algorithm primarily uses an improved baker transform method to process the image. In the image diffusion stage, the algorithm first uses the chaotic S-box method to process the encryption key. Secondly, an exclusive OR(XOR) operation is performed on the image and the encryption key to initially diffuse the image. Finally, the image is again diffused using the method of ortho XOR. Simulation analysis shows that the algorithm can achieve good encryption effect, simple and easy implementation, and good security. In the digital image communication transmission, it has good practical value.
基金Project supported by the Hi-Tech Research and Development Program (863) of China (No. 2006AA01Z226)the Scientific Research Foundation of Huazhong University of Science and Technol-ogy (No. 2006Z001B), China
摘要Using composite field arithmetic in Galois field can result in the compact Rijndael S-Box. However, the power con- sumption of this solution is too large to be used in resource-limited embedded systems. A full-custom hardware implementation of composite field S-Box is proposed for these targeted domains in this paper. The minimization of power consumption is implemented by optimizing the architecture of the composite field S-Box and using the pass transmission gate (PTG) to realize the logic functions of S-Box. Power simulations were performed using the netlist extracted from the layout. HSPICE simulation results indicated that the proposed S-Box achieves low power consumption of about 130 μW at 10 MHz using 0.25 μm/2.5 V technology, while the consumptions of the positive polarity reed-muller (PPRM) based S-Box and composite field S-Box based on the conventional CMOS logic style are about 240 μW and 420 μW, respectively. The simulations also showed that the presented S-Box obtains better low-voltage operating property, which is clearly relevant for applications like sensor nodes, smart cards and radio frequency identification (RFID) tags.
基金This work was supported by the National Natural Science Foundation of China(Grant No.92164101)the National Natural Science Foundation of China(Grant No.62171437)+2 种基金the Strategic Priority Research Program of the Chinese Academy of Sciences(Grant No.XDA18000000)Shanghai Science and Technology Committee(Grant No.21DZ1101000)the National Key R&D Program of China(Grant No.2021YFB0300400).
摘要Rapid single flux quantum(RSFQ)circuits are a kind of superconducting digital circuits,having properties of a natural gate-level pipelining synchronous sequential circuit,which demonstrates high energy efficiency and high throughput advantage.We find that the high-throughput and high-speed performance of RSFQ circuits can take the advantage of a hardware implementation of the encryption algorithm,whereas these are rarely applied to this field.Among the available encryption algorithms,the advanced encryption standard(AES)algorithm is an advanced encryption standard algorithm.It is currently the most widely used symmetric cryptography algorithm.In this work,we aim to demonstrate the SubByte operation of an AES-128 algorithm using RSFQ circuits based on the SIMIT Nb03 process.We design an AES S-box circuit in the RSFQ logic,and compare its operational frequency,power dissipation,and throughput with those of the CMOS-based circuit post-simulated in the same structure.The complete RSFQ S-box circuit costs a total of 42237 Josephson junctions with nearly 130 Gbps throughput under the maximum simulated frequency of 16.28 GHz.Our analysis shows that the frequency and throughput of the RSFQ-based S-box are about four times higher than those of the CMOS-based S-box.Further,we design and fabricate a few typical modules of the S-box.Subsequent measurements demonstrate the correct functioning of the modules in both low and high frequencies up to 28.8 GHz.
基金funded by Deanship of Scientific Research at Najran University under the Research Groups Funding Program Grant Code(NU/RG/SERC/12/3)also by Princess Nourah bint Abdulrahman University Researchers Supporting Project Number(PNURSP2023R333)Princess Nourah bint Abdulrahman University,Riyadh,Saudi Arabia.
摘要Securing digital image data is a key concern in today’s information-driven society.Effective encryption techniques are required to protect sensitive image data,with the Substitution-box(S-box)often playing a pivotal role in many symmetric encryption systems.This study introduces an innovative approach to creating S-boxes for encryption algorithms.The proposed S-boxes are tested for validity and non-linearity by incorporating them into an image encryption scheme.The nonlinearity measure of the proposed S-boxes is 112.These qualities significantly enhance its resistance to common cryptographic attacks,ensuring high image data security.Furthermore,to assess the robustness of the S-boxes,an encryption system has also been proposed and the proposed S-boxes have been integrated into the designed encryption system.To validate the effectiveness of the proposed encryption system,a comprehensive security analysis including brute force attack and histogram analysis has been performed.In addition,to determine the level of security during the transmission and storage of digital content,the encryption system’s Number of Pixel Change Rate(NPCR),and Unified Averaged Changed Intensity(UACI)are calculated.The results indicate a 99.71%NPCR and 33.51%UACI.These results demonstrate that the proposed S-boxes offer a significant level of security for digital content throughout its transmission and storage.
基金Sponsored by the National Natural Science Foundation of China(Grant No.61074192)the Beijing Natural Science Foundation(Grant No.4092040)the Natural Science Research of Henan Province Education Department(Grant No.2011B110002)
摘要A substitution box (S-box) plays an important role in cryptographic algorithms.The design of S-box using chaotic systems has attracted a great deal of attention in recent years.A new method for obtaining cryptographically strong S-boxes based on spatiotemporal chaotic system is proposed in this paper.The discretized Baker map and affine transformation are used orderly by an algorithm to shuffle the table generated by the spatiotemporal chaotic system.The cryptographical properties of these S-boxes such as bijection,nonlinearity,strict avalanche,output bits independence and equiprobable input /output XOR distribution are analyzed.The results of numerical analysis show that the S-box designed by this method can against several attacks and all the criteria for designing good S-box can be satisfied approximately.More strong S-boxes can be obtained by this method with the change of the original conditions or control parameters of the spatiotemporal chaos system.Furthermore,our approach is suitable for practical application in designing cryptosystem.
基金Supported by the National Natural Science Foundation of China (60473012)
摘要Multi-objective genetic algorithm is much suitable for solving multi-objective optimization problems. By use of Genetic algorithm, the optimization of S-boxes is explored in this paper. Results of the experiments show that, with heuristic mutation strategy, the algorithm has high searching efficiency and fast convergence speed. Meanwhile, we also have take the avalanche probability of S-boxes into account, besides nonlinearity and difference uniformity. Under this method, an effective genetic algorithm for 6×6 S-boxes is provided and a number of S-boxes with good cryptographic capability can be obtained.
基金This work was supported by the National Science and Technology Major Project of China(2017ZX01030301).
摘要A side-channel attack(SCA)-resistant AES S-box implementation is proposed,which is an improvement from the power-aware hiding(PAH)S-box but with higher security and a smaller area.We use the composite field approach and apply the PAH method to the inversion in the nonlinear kernel and a masking method to the other parts.In addition,a delaymatched enable control technique is used to suppress glitches in the masked parts.The evaluation results show that its area is contracted to 63.3%of the full PAH S-box,and its power-delay product is much lower than that of the masking implementation.The leakage assessment using simulation power traces concludes that it has no detectable leakage under t-test and that it at least can thwart the moment-correlation analysis using 665000 noiseless traces.
基金the National High Technology Research and Development Programme of China(Grant No2006AA01Z226)the Project(Grant No2006Z001B)the Scientific Research Foundation of Huazhong University of Science and Technology
摘要To obtain a low-power and compact implementation of the advanced encryption standard (AES) S- box, an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper. In the presented S-box, some improvements were made as follows. (1) Level-sensitive latches were inserted in data path to block the propagation Of the dynamic hazards, which lowered the power of data path circuit. (2) Operations of latches were controlled by latch controllers based on presented asynchronous sequence element: LC-element, which utilized static asymmetric C-element to construct a simple and power-efficient circuit structure. (3) Implementation of the data path circuit was a semi-custom standard-cell circuit on 0.25μm complementary mental oxide semiconductor (CMOS) process; and the full-custom design methodology was adopted in the handshake circuit design. Experimental results show that the resulting circuit achieves nearly 46% improvement with moderate area penalty ( 11.7% ) compared with the related composite field S-box in power performance. The presented S-box circuit can be a hardware intelli-gent property (IP) embedded in the targeted systems such as wireless sensor networks (WSN), smart-cards and radio frequency identification (RFID).
基金the National High Technology Research and Development Programme of China(No.2006AA01Z226)
摘要Substitution boxes (S-Boxes) in advanced encryption standard (AES) are vulnerable to attacks bypower analysis.The general S-Boxes masking schemes in circuit level need to adjust the design flow andlibrary databases.The masking strategies in algorithm level view each S-Box as an independent moduleand mask them respectively,which are costly in size and power for non-linear characteristic of S-Boxes.The new method uses dynamic inhomogeneous S-Boxes instead of traditional homogeneous S-Boxes,andarranges the S-Boxes randomly.So the power and data path delay of substitution unit become unpre-dictable.The experimental results demonstrate that this scheme takes advantages of the circuit character-istics of various S-Box implementations to eliminate the correlation between crypto operation and power.Itneeds less extra circuits and suits resource constrained applications.