In this paper,a comprehensive evaluation on the silicon/silicon carbide(Si/SiC)hybrid switch is performed through experimental tests in terms of both electrical performance and robustness under extreme stresses.Based ...In this paper,a comprehensive evaluation on the silicon/silicon carbide(Si/SiC)hybrid switch is performed through experimental tests in terms of both electrical performance and robustness under extreme stresses.Based on the optional turn-on and turn-off delay times under the efficiency control mode obtained from the double-pulse test(DPT),both nondestructive and destructive single-pulse avalanche tests are conducted on the Si/SiC hybrid switch as well as on the two discrete device branches inside the hybrid switch.In addition,the avalanche voltage,critical avalanche energy,and peak avalanche current,which intrinsically characterize the unclamped-inductive-switching(UIS)avalanche characteristics,are carefully examined.In this way,the physical factors dominating the UIS characteristics of the hybrid switch,thus limiting its single-pulse avalanche withstand capability,are specifically and comprehensively identified;the underlying physical mechanisms are analyzed and revealed in depth,and how the gate control sequence affects the UIS characteristics of the hybrid switch is extensively investigated.We additionally carry out short-circuit(SC)tests under the fault-under-load(FUL)condition and perform a parallel in-depth analysis to experimentally determine which branch dominates the SC withstand capability of the hybrid switch.Our experimental study indicates that,for both SC robustness and single-pulse avalanche capability,the limiting factor is a single device branch among the two parallel discrete devices,and the UIS behavior is sensitive to the variation of the gate turn-off delay time Toff_delay.The study conducted in this paper not only provides deep academic insights into the electrical performance and reliability of the Si/SiC hybrid switch,but also offers fundamental theoretical principles and technical evidence to support its more efficient and long-term reliable applications of the hybrid switch in the industrial fields.展开更多
The Al/Si/SiC composites with medium volume fraction for electronic packaging were fabricated by gas pressure infiltration.On the premise of keeping the machinability of the composites,the silicon carbide particles,wh...The Al/Si/SiC composites with medium volume fraction for electronic packaging were fabricated by gas pressure infiltration.On the premise of keeping the machinability of the composites,the silicon carbide particles,which have the similar size with silicon particles(average 13 μm),were added to replace silicon particles of same volume fraction,and microstructure and properties of the composites were investigated.The results show that reinforcing particles are distributed uniformly and no apparent pores are observed in the composites.It is also observed that higher thermal conductivity(TC) and flexural strength will be obtained with the addition of SiC particles.Meanwhile,coefficient of thermal expansion(CTE) changes smaller than TC.Models for predicting thermal properties were also discussed.Equivalent effective conductivity(EEC) was proposed to make H-J model suitable for hybrid particles and multimodal particle size distribution.展开更多
Si/SiC ceramic composite and lnvar alloy were successfidly joined by vacuum brazing using Ti5OCu-W filler metals into which W was added to release the thermal stress of the brazed joint. Microstructures of the brazed ...Si/SiC ceramic composite and lnvar alloy were successfidly joined by vacuum brazing using Ti5OCu-W filler metals into which W was added to release the thermal stress of the brazed joint. Microstructures of the brazed joints were irwestigated by scanning electron micrascope (SEM) and energy dispersive spectrometer (EDS). The mechanical properties of the brazed joints were measured by shearing tests. The results showed that the brazed joints were composed of Ti-Cu phase, W phase and Ti-Si phase. W had no effect on the wettability and mobility of the .filler metals. The growth of Ti2 Cu phase was restrained, and the reaction between ceramic composite and filler metals was weakened. The specimen, brazed at 970°C for 5 rain, had the maximum shear strength of 108 MPa at room temperature.展开更多
A novel silicon carbide(SiC) on silicon(Si) heterojunction lateral double-diffused metal-oxide semiconductor fieldeffect transistor with p-type buried layer(PBL Si/SiC LDMOS) is proposed in this paper for the first ti...A novel silicon carbide(SiC) on silicon(Si) heterojunction lateral double-diffused metal-oxide semiconductor fieldeffect transistor with p-type buried layer(PBL Si/SiC LDMOS) is proposed in this paper for the first time.The heterojunction has breakdown point transfer(BPT) characteristics,and the BPT terminal technology is used to increase the breakdown voltage(BV) of Si/SiC LDMOS with the deep drain region.In order to further optimize the surface lateral electric field distribution of Si/SiC LDMOS with the deep drain region,the p-type buried layer is introduced in PBL Si/SiC LDMOS.The vertical electric field is optimized by Si/SiC heterojunction and the surface lateral electric field is optimized by the p-type buried layer,which greatly improves the BV of device and alleviates the relationship between BV and specific on-resistance(Ron,sp).Through TCAD simulation,when the drift region length is 20 μm,the BV is significantly improved from 249 V for the conventional Si LDMOS to 440 V for PBL Si/SiC LDMOS,increased by 77%;And the BV is improved from 384 V for Si/SiC LDMOS with the deep drain region to 440 V for the proposed structure,increased by 15%.The figure-of-merit(FOM) of the Si/SiC LDMOS with the deep drain region and PBL Si/SiC LDMOS are 4.26 MW/cm2 and 6.37 MW/cm2,respectively.For the PBL Si/SiC LDMOS with the drift length of 20 μm,the maximum FOM is 6.86 MW/cm2.The PBL Si/SiC LDMOS breaks conventional silicon limit.展开更多
基金supported in part by the Anhui Provincial Natural Science Foundation Youth Project(Category C)under Grant No.2508085QE184the Opening Project of Key Laboratory of Power Electronics and Motion Control of Anhui Higher Education Institutions under Grant No.PEMC24004+1 种基金the Anhui University of Technology Young Teachers Research Fund under Grant No.QZ202412the Scientific Research Startup Fund for Introduced Talents of Anhui University of Technology under Grant No.QD202340.
摘要In this paper,a comprehensive evaluation on the silicon/silicon carbide(Si/SiC)hybrid switch is performed through experimental tests in terms of both electrical performance and robustness under extreme stresses.Based on the optional turn-on and turn-off delay times under the efficiency control mode obtained from the double-pulse test(DPT),both nondestructive and destructive single-pulse avalanche tests are conducted on the Si/SiC hybrid switch as well as on the two discrete device branches inside the hybrid switch.In addition,the avalanche voltage,critical avalanche energy,and peak avalanche current,which intrinsically characterize the unclamped-inductive-switching(UIS)avalanche characteristics,are carefully examined.In this way,the physical factors dominating the UIS characteristics of the hybrid switch,thus limiting its single-pulse avalanche withstand capability,are specifically and comprehensively identified;the underlying physical mechanisms are analyzed and revealed in depth,and how the gate control sequence affects the UIS characteristics of the hybrid switch is extensively investigated.We additionally carry out short-circuit(SC)tests under the fault-under-load(FUL)condition and perform a parallel in-depth analysis to experimentally determine which branch dominates the SC withstand capability of the hybrid switch.Our experimental study indicates that,for both SC robustness and single-pulse avalanche capability,the limiting factor is a single device branch among the two parallel discrete devices,and the UIS behavior is sensitive to the variation of the gate turn-off delay time Toff_delay.The study conducted in this paper not only provides deep academic insights into the electrical performance and reliability of the Si/SiC hybrid switch,but also offers fundamental theoretical principles and technical evidence to support its more efficient and long-term reliable applications of the hybrid switch in the industrial fields.
基金Project (60776019) supported by the National Natural Science Foundation of ChinaProject (61-TP-2010) supported by the Research Fund of the State Key Laboratory of Solidification Processing (NWPU),China
摘要The Al/Si/SiC composites with medium volume fraction for electronic packaging were fabricated by gas pressure infiltration.On the premise of keeping the machinability of the composites,the silicon carbide particles,which have the similar size with silicon particles(average 13 μm),were added to replace silicon particles of same volume fraction,and microstructure and properties of the composites were investigated.The results show that reinforcing particles are distributed uniformly and no apparent pores are observed in the composites.It is also observed that higher thermal conductivity(TC) and flexural strength will be obtained with the addition of SiC particles.Meanwhile,coefficient of thermal expansion(CTE) changes smaller than TC.Models for predicting thermal properties were also discussed.Equivalent effective conductivity(EEC) was proposed to make H-J model suitable for hybrid particles and multimodal particle size distribution.
摘要Si/SiC ceramic composite and lnvar alloy were successfidly joined by vacuum brazing using Ti5OCu-W filler metals into which W was added to release the thermal stress of the brazed joint. Microstructures of the brazed joints were irwestigated by scanning electron micrascope (SEM) and energy dispersive spectrometer (EDS). The mechanical properties of the brazed joints were measured by shearing tests. The results showed that the brazed joints were composed of Ti-Cu phase, W phase and Ti-Si phase. W had no effect on the wettability and mobility of the .filler metals. The growth of Ti2 Cu phase was restrained, and the reaction between ceramic composite and filler metals was weakened. The specimen, brazed at 970°C for 5 rain, had the maximum shear strength of 108 MPa at room temperature.
基金Project supported in part by the Science Foundation for Distinguished Young Scholars of Shaanxi Province,China(Grant No.2018JC-017)the 111 Project(Grant No.B12026)。
摘要A novel silicon carbide(SiC) on silicon(Si) heterojunction lateral double-diffused metal-oxide semiconductor fieldeffect transistor with p-type buried layer(PBL Si/SiC LDMOS) is proposed in this paper for the first time.The heterojunction has breakdown point transfer(BPT) characteristics,and the BPT terminal technology is used to increase the breakdown voltage(BV) of Si/SiC LDMOS with the deep drain region.In order to further optimize the surface lateral electric field distribution of Si/SiC LDMOS with the deep drain region,the p-type buried layer is introduced in PBL Si/SiC LDMOS.The vertical electric field is optimized by Si/SiC heterojunction and the surface lateral electric field is optimized by the p-type buried layer,which greatly improves the BV of device and alleviates the relationship between BV and specific on-resistance(Ron,sp).Through TCAD simulation,when the drift region length is 20 μm,the BV is significantly improved from 249 V for the conventional Si LDMOS to 440 V for PBL Si/SiC LDMOS,increased by 77%;And the BV is improved from 384 V for Si/SiC LDMOS with the deep drain region to 440 V for the proposed structure,increased by 15%.The figure-of-merit(FOM) of the Si/SiC LDMOS with the deep drain region and PBL Si/SiC LDMOS are 4.26 MW/cm2 and 6.37 MW/cm2,respectively.For the PBL Si/SiC LDMOS with the drift length of 20 μm,the maximum FOM is 6.86 MW/cm2.The PBL Si/SiC LDMOS breaks conventional silicon limit.