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Single-event effects induced by medium-energy protons in 28 nm system-on-chip 认领 引用 被引量：5
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作者 Wei-Tao Yang Qian Yin +6 位作者 Yang Li Gang Guo Yong-Hong Li Chao-Hui He Yan-Wen Zhang Fu-Qiang Zhang Jin-Hua Han 《Nuclear Science and Techniques》 SCIE EI CAS CSCD 2019年第10期55-62,共8页
Single-event effects(SEEs)induced by mediumenergy protons in a 28 nm system-on-chip(SoC)were investigated at the China Institute of Atomic Energy.An on-chip memory block was irradiated with 90 MeV and 70 MeV protons,r... Single-event effects(SEEs)induced by mediumenergy protons in a 28 nm system-on-chip(SoC)were investigated at the China Institute of Atomic Energy.An on-chip memory block was irradiated with 90 MeV and 70 MeV protons,respectively.Single-bit upset and multicell upset events were observed,and an uppermost number of nine upset cells were discovered in the 90 MeV proton irradiation test.The results indicate that the SEE sensitivities of the 28 nm SoC to the 90 MeV and 70 MeV protons were similar.Cosmic Ray Effects on Micro-Electronics Monte Carlo simulations were analyzed,and it demonstrates that protons can induce effects in a 28 nm SoC if their energies are greater than 1.4 MeV and that the lowest corresponding linear energy transfer was 0.142 MeV cm^2 mg^-1.The similarities and discrepancies of the SEEs induced by the 90 MeV and 70 MeV protons were analyzed. 展开更多
关键词 Single-event effect Proton System-on-chip
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Investigation of single event effect in 28-nm system-on-chip with multi patterns 认领 引用 被引量：5
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作者 Wei-Tao Yang Yong-Hong Li +8 位作者 Ya-Xin Guo Hao-Yu Zhao Yang Li Pei Li Chao-Hui He Gang Guo Jie Liu Sheng-Sheng Yang Heng An 《Chinese Physics B》 SCIE EI CAS CSCD 2020年第10期573-577,共5页
Single event effects (SEEs) in a 28-nm system-on-chip (SoC) were assessed using heavy ion irradiations, and susceptibilities in different processor configurations with data accessing patterns were investigated. The pa... Single event effects (SEEs) in a 28-nm system-on-chip (SoC) were assessed using heavy ion irradiations, and susceptibilities in different processor configurations with data accessing patterns were investigated. The patterns included the sole processor (SP) and asymmetric multiprocessing (AMP) patterns with static and dynamic data accessing. Single event upset (SEU) cross sections in static accessing can be more than twice as high as those of the dynamic accessing, and processor configuration pattern is not a critical factor for the SEU cross sections. Cross section interval of upset events was evaluated and the soft error rates in aerospace environment were predicted for the SoC. The tests also indicated that ultra-high linear energy transfer (LET) particle can cause exception currents in the 28-nm SoC, and some even are lower than the normal case. 展开更多
关键词 system-on-chip heavy ion single event effect
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Random testing for system-level functional verification of system-on-chip 认领 引用 被引量：4
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作者 Ma Qinsheng Cao Yang +1 位作者 Yang Jun Wang Min 《Journal of Systems Engineering and Electronics》 SCIE EI 2009年第6期1378-1383,共6页
In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity o... In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity of this method is proven theoretically.Specifically, testcases are generated according to many approaches of randomization.Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language.Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily.The comparison method is put to use in the evaluation approach of the testing validity.The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing.The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible. 展开更多
关键词 VLSI circuit verification random process function testing system-on-chip system-level.
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ADVANCED FREQUENCY-DIRECTED RUN-LENTH BASED CODING SCHEME ON TEST DATA COMPRESSION FOR SYSTEM-ON-CHIP 认领 引用 被引量：1
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作者 张颖 吴宁 葛芬 《Transactions of Nanjing University of Aeronautics and Astronautics》 EI 2012年第1期77-83,共7页
Test data compression and test resource partitioning （TRP） are essential to reduce the amount of test data in system-on-chip testing. A novel variable-to-variable-length compression codes is designed as advanced fre... Test data compression and test resource partitioning （TRP） are essential to reduce the amount of test data in system-on-chip testing. A novel variable-to-variable-length compression codes is designed as advanced fre- quency-directed run-length （AFDR） codes. Different [rom frequency-directed run-length （FDR） codes, AFDR encodes both 0- and 1-runs and uses the same codes to the equal length runs. It also modifies the codes for 00 and 11 to improve the compression performance. Experimental results for ISCAS 89 benchmark circuits show that AFDR codes achieve higher compression ratio than FDR and other compression codes. 展开更多
关键词 test data compression FDR codes test resource partitioning system-on-chip
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Scheduling method based on virtual flattened architecture for Hierarchical system-on-chip 认领 引用
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作者 张冬 张金艺 +1 位作者 杨晓冬 杨毅 《Journal of Shanghai University(English Edition)》 2009年第6期433-437,共5页
As the technology of IP-core-reused has been widely used, a lot of intellectual property （IP） cores have been embedded in different layers of system-on-chip （SOC）. Although the cycles of development and overhead a... As the technology of IP-core-reused has been widely used, a lot of intellectual property （IP） cores have been embedded in different layers of system-on-chip （SOC）. Although the cycles of development and overhead are reduced by this method, it is a challenge to the SOC test. This paper proposes a scheduling method based on the virtual flattened architecture for hierarchical SOC, which breaks the hierarchical architecture to the virtual flattened one. Moreover, this method has more advantages compared with the traditional one, which tests the parent cores and child cores separately. Finally, the method is verified by the ITC＇02 benchmark, and gives good results that reduce the test time and overhead effectively. 展开更多
关键词 system-on-chip test virtual flat hierarchical SOC test scheduling
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A 130-nm ferroelectric nonvolatile system-on-chip for internet of things 认领 引用
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作者 Zhiyi Yu 《Journal of Semiconductors》 CAS CSCD 2019年第2期6-6,共1页
IEEE J.Solid-State Circuits,2019,doi:10.1109/JSSC.2018.2884349Nonvolatile processor(NVP)is promising for energy-harvesting-powered internet-of-things(IoT)devices,owing to its unique capability to sustain computation p... IEEE J.Solid-State Circuits,2019,doi:10.1109/JSSC.2018.2884349Nonvolatile processor(NVP)is promising for energy-harvesting-powered internet-of-things(IoT)devices,owing to its unique capability to sustain computation progress over power outages.Recently. 展开更多
关键词 NVP A 130-nm ferroelectric nonvolatile system-on-chip for internet of things
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Reconfigurable Ultrasonic Testing System Development Using Programmable Analog Front-End and Reconfigurable System-on-Chip Hardware 认领 引用
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作者 Pramod Govindan Vidya Vasudevan +1 位作者 Thomas Gonnot Jafar Saniie 《Circuits and Systems》 2015年第7期161-171,共11页
Ultrasonic testing systems have been extensively used in medical imaging and non-destructive testing applications. Generally, these systems aim at a particular application or target material. To make these systems por... Ultrasonic testing systems have been extensively used in medical imaging and non-destructive testing applications. Generally, these systems aim at a particular application or target material. To make these systems portable and more adaptable to the test environments, this study presents a reconfigurable ultrasonic testing system (RUTS), which possesses dynamic reconfiguration capabilities. RUTS consists a fully programmable Analog Front-End (AFE), which facilitates beamforming and signal conditioning for variety of applications. RUTS AFE supports up to 8 transducers for phased-array implementation. Xilinx Zynq System-on-Chip (SoC) based Zedboard provides the back-end processing of RUTS. The powerful ARM embedded processor available within Zynq SoC manages the ultrasonic data acquisition/processing and overall system control, which makes RUTS a unique platform for the ultrasonic researchers to experiment and evaluate a wide range of real-time ultrasonic signal processing applications. This Linux-based system is utilized for ultra-sonic data compression implementation providing a versatile environment for further development of ultrasonic imaging and testing system. Furthermore, this study demonstrates the capabilities of RUTS by performing ultrasonic data acquisition and data compression in real-time. Thus, this reconfigurable system enables ultrasonic designers and researchers to efficiently prototype different experiments and to incorporate and analyze high performance ultrasonic signal and image processing algorithms. 展开更多
关键词 Dynamic Reconfiguration System-on-Chip Analog Front-End Ultrasonic Imaging
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A Low-Cost Open-Loop Fractional Output Divider for Audio System-on-Chip in 180 nm CMOS 认领 引用
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作者 Zhaoquan Zeng Martin Mallinson +3 位作者 Liang He Emily Slous Lijiao Gong Ning Zhang 《Tsinghua Science and Technology》 SCIE EI CAS CSCD 2026年第2期1031-1043,共13页
This paper introduces aΔ-Σfractional output divider(FOD)designed for audio system-on-chip(SoC)applications with low design and implementation cost.In contrast to conventional FOD design methodologies that utilize a ... This paper introduces aΔ-Σfractional output divider(FOD)designed for audio system-on-chip(SoC)applications with low design and implementation cost.In contrast to conventional FOD design methodologies that utilize a multi-modulus divider(MMD)or a multi-phase multiplexer(MPM)based divider incorporating complex jitter filters,the proposed FOD adopts a feed-forward architecture employing simple circuit building blocks.It leverages aΔ-Σdigital-to-frequency converter(DFC)to generate fractionally synthesized output frequencies,eliminating the synchronous constraint associated with MMD and MPM methods.The DFC employs a fully-synthesizableΔ-Σmodulator and resistor-2 resistor(R-2R)digital-to-analog converter to generate 4-level waveform patterns containing the desired output frequency information.These patterns are then processed through an integrator and a zero-crossing detector to reconstruct the fractionally divided output clock signal.Furthermore,to minimize jitter,a simple edge combiner-based jitter filter is cascaded with the DFC output.Implemented in 180 nm digital complementary metal-oxide-semiconductor process and operating at 1.2 V supply voltage,the proposed FOD offers an output frequency range of 500 kHz to 45 MHz,with Nmin=FIN/FOUT=4.Specifically,It divides a 26 MHz input to generate a 6.144 MHz(128fs=128×44.1 kHz)output,exhibiting a root-mean-square jitter of 3.68 ps,while consuming 0.22 mW of power. 展开更多
关键词 fractional output divider digital-to-frequency converter ∆-Σmodulation jitter filter audio system-on-chip
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Data Fusion with Genetic Algorithm Based Lifetime Prediction for Dependable Multi-Processor System-on-Chips 认领 引用
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作者 Yong Zhao Longkun Guo Xiaoyan Zhang 《Tsinghua Science and Technology》 SCIE EI CAS CSCD 2023年第6期1041-1049,共9页
With the prevalence of big-data technology,intricate,nanoscale Multi-Processor System-on-Chips(MP-SoCs)have been used in various safety-critical applications.However,with no extra countermeasures taken,this widespread... With the prevalence of big-data technology,intricate,nanoscale Multi-Processor System-on-Chips(MP-SoCs)have been used in various safety-critical applications.However,with no extra countermeasures taken,this widespread use of MP-SoCs can lead to an undesirable decrease in their dependability.This study presents a promising approach using a group of Embedded Instruments(EIs)inside a processor core for health monitoring.Multiple health monitoring datasets obtained from the employed EIs are sampled and collated via the implemented experiment and thereafter used for conducting its remaining useful lifetime prognostics.This enables MP-SoCs to undertake preventive self-repair,thus realizing a zero mean downtime system and ensuring improved dependability.In addition,a principal component analysis based algorithm is designed for realizing the EI data fusion.Subsequently,a genetic algorithm based degradation optimization is employed to create a lifetime prediction model with respect to the processor. 展开更多
关键词 data fusion genetic algorithm lifetime prediction health monitor multi-core System-on-Chips(SoCs) embedded instruments
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REVIEW OF ADVANCED FPGA ARCHITECTURES AND TECHNOLOGIES 认领 引用 被引量：8
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作者 Yang Haigang Zhang Jia +1 位作者 Sun Jiabin Yu Le 《Journal of Electronics(China)》 2014年第5期371-393,共23页
Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid developme... Field Programmable Gate Array(FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development. 展开更多
关键词 Field Programmable Gate Array(FPGA) Microchip architecture Programmable logic device System-on-Chip(SoC)
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Stepping Control Method of Linear Displacement Mechanism Driven by TRUM Based on PSoC 认领 引用 被引量：2
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作者 王军平 刘卫东 +2 位作者 朱华 李亦君 李建军 《Transactions of Nanjing University of Aeronautics and Astronautics》 EI CSCD 2015年第2期226-231,共6页
A method based on programmable system-on-chip(PSoC)is proposed to realize high resolution stepping motion control of liner displacement mechanism driven by traveling wave rotary ultrasonic motors(TRUM).Intelligent con... A method based on programmable system-on-chip(PSoC)is proposed to realize high resolution stepping motion control of liner displacement mechanism driven by traveling wave rotary ultrasonic motors(TRUM).Intelligent controller of stepping ultrasonic motor consists of PSoC microprocessor.Continuous square wave signal is sent out by the pulse width modulator(PWM)module inside PSoC,and converted into sinusoidal signal which is essential to the motor′s normal working by power amplifier circuit.Subsequently,signal impulse transmission is realized by the counter control break,and the stepping motion of linear displacement mechanism based on TRUM is achieved.Running status of the ultrasonic motor is controlled by an upper computer.Control command is sent to PSoC through serial communication circuit of RS-232.Relative program and control interface are written in LabView.Finally the mechanism is tested by XL-80 laser interferometer.Test results show that the mechanism can provide a stable motion and a fixed step pitch with the displacement resolution of 6nm. 展开更多
关键词 programmable system-on-chip(PSoC) ultrasonic motor impulse transmission upper computer
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A front-end automation tool supporting design, verification and reuse of SOC 认领 引用 被引量：4
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作者 严晓浪 余龙理 王界兵 《Journal of Zhejiang University Science》 2004年第9期1102-1105,共4页
This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog... This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms. 展开更多
关键词 System-On-Chip Verilog HDL Verification Reuse
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Macroblock-level decoding and deblocking method and its pipeline implementation in H.264 decoder SOC design 认领 引用 被引量：1
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作者 WANG Shu-hui LIN Tao LIN Zheng-hui 《Journal of Zhejiang University-SCIENCE A》 SCIE EI CAS 2007年第1期36-41,共6页
This paper presents a macroblock-level (MB-level) decoding and deblocking method for supporting the flexible macroblock ordering (FMO) and arbitrary slice ordering (ASO) bit streams in H.264 decoder and its SOC/ASIC i... This paper presents a macroblock-level (MB-level) decoding and deblocking method for supporting the flexible macroblock ordering (FMO) and arbitrary slice ordering (ASO) bit streams in H.264 decoder and its SOC/ASIC implementation. By searching the slice containing the current macroblock in the bit stream and switching slices correctly, MBs can be decoded in the raster scan order, while the decoding process can immediately begin as long as the slice containing the current MB is available. This architectural modification enables the MB-level decoding and deblocking 3-stage pipeline, and saves about 20% of SDRAM bandwidth. Implementation results showed that the design achieves real-time decoding of 1080HD (1920×1088@30 fps) at a system clock of 166 MHz. 展开更多
关键词 Flexible macroblock ordering （FMO） Arbitrary slice ordering （ASO） System-on-chip （SOC） Raster scan order Pipeline
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CORE-UNIFIED SOC TEST DATA COMPRESSION AND APPLICATION 认领 引用
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作者 Yi Maoxiang Guo Xueying +2 位作者 Liang Huaguo Wang Wei Zhang Lei 《Journal of Electronics(China)》 2010年第1期79-87,共9页
The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are un... The pattern run-length coding test data compression approach is extended by introducing don't care bit(x) propagation strategy into it.More than one core test sets for testing core-based System-on-Chip(SoC) are unified into a single one,which is compressed by the extended coding technique.A reconfigurable scan test application mechanism is presented,in which test data for multiple cores are scanned and captured jointly to make SoC test application more efficient with low hardware overhead added.The proposed union test technique is applied to an academic SoC embedded by six large ISCAS'89 benchmarks,and to an ITC' 02 benchmark circuit.Experiment results show that compared with the existing schemes in which a core test set is compressed and applied independently of other cores,the proposed scheme can not only improve test data compression/decompression,but also reduce the redundant shift and capture cycles during scan testing,decreasing SoC test application time effectively. 展开更多
关键词 System-on-Chip(SoC) Test application time Pattern run-length X-propagation Union test Reconfiguration
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Designing cost-effective network-on-chip by dual-channel access mechanism 认领 引用
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作者 Shijun Lin Jianghong Shi Huihuang Chen 《Journal of Systems Engineering and Electronics》 SCIE EI CSCD 2011年第4期557-564,共8页
A dual-channel access mechanism to overcome the drawback of traditional single-channel access mechanism for network-on-chip(NoC)is proposed.In traditional single-channel access mechanism,every Internet protocol(IP)has... A dual-channel access mechanism to overcome the drawback of traditional single-channel access mechanism for network-on-chip(NoC)is proposed.In traditional single-channel access mechanism,every Internet protocol(IP)has only one chan-nel to access the on-chip network.When the network is relatively idle,the injection rate is too small to make good use of the network resource.When the network is relatively busy,the ejection rate is so small that the packets in the network cannot leave immediately,and thus the probability of congestion is increased.In the dual-channel access mechanism,the injection rate of IP and the ejection rate of the network are increased by using two optional channels in network interface(NI)and local port of routers.Therefore,the communication performance is improved.Experimental results show that compared with traditional single-channel access mechanism,the proposed scheme greatly increases the throughput and cuts down the average latency with reasonable area increase. 展开更多
关键词 network-on-chip(NoC) system-on-chip(SoC) singlechannel access dual-channel access.
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Area-time associated test cost model for SoC and lower bound of test time 认领 引用
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作者 张金艺 翁寒一 +1 位作者 黄徐辉 蔡万林 《Journal of Shanghai University(English Edition)》 2011年第1期43-48,共6页
A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test an... A novel test access mechanism （TAM） architecture with multi test-channel （TC） based on IEEE Standard 1500 is proposed instead of the traditional sub-TAM structure. The cost model of an area-time associated test and the corresponding lower bound of system-on-chip （SoC） test time are established based on this TAM architecture. The model provides a more reliable method to control the SoC scheduling and reduces the complexity in related algorithm research. The result based on the area time associated test cost model has been validated using the ITC02 test benchmark. 展开更多
关键词 system-on-chip design for testability （SoC DriP） test cost test time lower bound
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生化微传感SOC片内嵌入ADC的设计与实现 认领 引用
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作者 蔺增金 杨海钢 《电子器件》 CAS 2007年第3期733-737,共5页
首先根据生化微传感SOC的应用场合和微传感器的特点,选定CR SAR ADC作为片内嵌入类型;基于SOC的标准CMOS工艺实现和低功耗的设计目标,分别进行了电容阵列、比较器、开关阵列和SAR控制逻辑等组成单元全定制原理图、版图设计,实现了片内嵌... 首先根据生化微传感SOC的应用场合和微传感器的特点,选定CR SAR ADC作为片内嵌入类型;基于SOC的标准CMOS工艺实现和低功耗的设计目标,分别进行了电容阵列、比较器、开关阵列和SAR控制逻辑等组成单元全定制原理图、版图设计,实现了片内嵌入10位ADC的整体芯片.流片实测结果DNL、INL最大值分别为+/-1.0LSB、+/-1.5LSB,功耗仅为4.62mW,满足生化微传感SOC数据转换的片内嵌入要求. 展开更多
关键词 生化微传感器 SOC(system-on-chip) 片内嵌入A/D转换器 全差 分自置零比较器
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Gradual refinement for application-specific MPSoC design from Simulink model to RTL implementation 认领 引用 被引量：1
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作者 Kai HUANG Xiao-lang YAN +6 位作者 Sang-il HAN Soo-ik CHAE Ahmed A. JERRAYA Katalin POPOVICI Xavier GUERIN Lisane BRISOLARA Luigi CARRO 《Journal of Zhejiang University-SCIENCE A》 SCIE EI CAS 2009年第2期151-164,共14页
The application-specific multiprocessor system-on-chip(MPSoC) architecture is becoming an attractive solution to deal with increasingly complex embedded applications,which require both high performance and flexible pr... The application-specific multiprocessor system-on-chip(MPSoC) architecture is becoming an attractive solution to deal with increasingly complex embedded applications,which require both high performance and flexible programmability. As an effective method for MPSoC development,we present a gradual refinement flow starting from a high-level Simulink model to a synthesizable and executable hardware and software specification. The proposed methodology consists of five different abstract levels:Simulink combined algorithm and architecture model(CAAM),virtual architecture(VA),transactional accurate architecture(TA),virtual prototype(VP) and field-programmable gate array(FPGA) emulation. Experimental results of Motion-JPEG and H.264 show that the proposed gradual refinement flow can generate various MPSoC architectures from an original Simulink model,allowing processor,communication and tasks design space exploration. 展开更多
关键词 Multiprocessor system-on-chip （MPSoC） design Refinement Simulink SystemC Motion-JPEG H.264
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三种SoC片上总线的分析与比较 认领 引用 被引量：11
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作者 张丽媛 章军 陈新华 《山东科技大学学报（自然科学版）》 CAS 2005年第2期66-69,共4页
随着以IP核复用为基础的SoC设计技术的发展,工业界及研究组织正积极从事相关IP互联标准方案的制定工作。本文介绍了目前SoC设计中常用的三种片上总线标准,即IBM公司的CoreConnect总线、ARM公司的AMBA总线和OCPIP组织的OCP总线,重点分析... 随着以IP核复用为基础的SoC设计技术的发展,工业界及研究组织正积极从事相关IP互联标准方案的制定工作。本文介绍了目前SoC设计中常用的三种片上总线标准,即IBM公司的CoreConnect总线、ARM公司的AMBA总线和OCPIP组织的OCP总线,重点分析和比较了它们的特性,并针对它们不同的特点,阐述其合适的应用领域。 展开更多
关键词 SoC(System-on-Chip) 片上总线,IP(Intellectual Property)核 可复用设计
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FlexMEMS-enabled hetero-integration for monolithic FBAR-above-IC oscillators 认领 引用 被引量：1
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作者 Chuanhai Gao Menglun Zhang Yuan Jiang 《Nanotechnology and Precision Engineering》 EI CAS CSCD 2019年第3期105-109,共5页
In this work,a monolithic oscillator chip is heterogeneously integrated by a film bulk acoustic resonator(FBAR)and a complementary metal-oxide-semiconductor(CMOS)chip using FlexMEMS technology.In the 3 D-stacked integ... In this work,a monolithic oscillator chip is heterogeneously integrated by a film bulk acoustic resonator(FBAR)and a complementary metal-oxide-semiconductor(CMOS)chip using FlexMEMS technology.In the 3 D-stacked integrated chip,the thin-film FBAR sits directly over the CMOS chip,between which a 4μm-thick SU-8 layer provides a robust adhesion and acoustic reflection cavity.The proposed system-on-chip(SoC)integration features a simple fabrication process,small size,and excellent performance.The oscillator outputs 2.024 GHz oscillations of-13.79 dB m and exhibits phase noises of-63,-120,and-136 dB c/Hz at 1 kHz,100 kHz,and far-from-carrier offset,respectively.FlexMEMS technology guarantees compact and accurate assembly,process compatibility,and high performance,thereby demonstrating its great potential in SoC hetero-integration applications. 展开更多
关键词 FlexMEMS Hetero-integration Film bulk acoustic resonator System-on-chip Oscillator
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