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Design of a high-voltage radiation-tolerant driver with a novel comparator and drain-surrounding-source structure 认领 引用 被引量：1
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作者 Wei Huang Hong-Xia Liu Xing-Guo Gao 《Nuclear Science and Techniques》 SCIE EI CAS CSCD 2025年第7期34-43,共10页
This article introduces a novel 20 V radiation-hardened high-voltage metal-oxide-semiconductor field-effect transistor(MOSFET)driver with an optimized input circuit and a drain-surrounding-source(DSS)structure.The inp... This article introduces a novel 20 V radiation-hardened high-voltage metal-oxide-semiconductor field-effect transistor(MOSFET)driver with an optimized input circuit and a drain-surrounding-source(DSS)structure.The input circuit of a conventional inverter consists of a thick-gate-oxide n-type MOSFET(NMOS).These conventional drivers can tolerate a total ionizing dose(TID)of up to 100 krad(Si).In contrast,the proposed comparator input circuit uses both a thick-gate-oxide p-type MOSFET(PMOS)and thin-gate-oxide NMOS to offer a high input voltage and higher TID tolerance.Because the thick-gate-oxide PMOS and thin-gate-oxide NMOS collectively provide better TID tolerance than the thick-gate-oxide NMOS,the circuit exhibits enhanced TID tolerance of>300 krad(Si).Simulations and experimental date indicate that the DSS structure reduces the probability of unwanted parasitic bipolar junction transistor activation,yielding a better single-event effect tolerance of over 81.8 MeVcm2mg-1.The innovative strategy proposed in this study involves circuit and layout design optimization,and does not require any specialized process flow.Hence,the proposed circuit can be manufactured using common commercial 0.35μm BCD processes. 展开更多
关键词 Total ionizing dose(TID) Single-event burnout(SEB) High-voltage driver Comparator input unit Drain-surrounding-source ring structure
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Novel Design of Low-power Multiplex Differential Voltage Comparators 认领 引用
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作者 WANG Hong-yi LAI Xin-quan LI Yu-shan 《Semiconductor Photonics and Technology》 2007年第1期1-6,共6页
A novel design of multiplex differential voltage comparators(MDVC) is presented for reducing current and power dissipation. According to the special properties of relational operation and logical operation, parts of t... A novel design of multiplex differential voltage comparators(MDVC) is presented for reducing current and power dissipation. According to the special properties of relational operation and logical operation, parts of the comparators are redundant in some instances, and thus can be turned off. By selecting and switching the current routes, several effective differential pairs are biased by a single tail current stage-by-stage and the redundant comparators are turned off by cutting their tail currents. As a result, the quiescent current and power consumption are greatly decreased. The switching of current is achieved by the input differential pair transistors themselves and hence no extra switches are required. When a MDVC is used in a flash analog-to-digital converter(ADC), its current dissipation is much lower than that of the conventional comparators. This architecture can also be used in window-comparators, maximum or minimum comparators, and comparators for logical operations. The power dissipation in all these cases could be reduced significantly. 展开更多
关键词 low-power comparators multiplex comparators window comparators flash ADC switchedcurrent
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THE DESIGN OF THE HIGH SPEED AND HIGH PRECISION LATCHING VOLTAGE COMPARATOR ZJ03 认领 引用 被引量：1
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作者 毛培法 江来喜 《Journal of Electronics(China)》 1991年第2期163-168,共6页
The design of a new type of latching voltage comparator ZJ03 is described.Thecommon voltage comparators consist of multistage DC amplifiers,for which it is difficult to realizehigh speed and high precision.The ZJ03 co... The design of a new type of latching voltage comparator ZJ03 is described.Thecommon voltage comparators consist of multistage DC amplifiers,for which it is difficult to realizehigh speed and high precision.The ZJ03 comparator contains a controlled positive feedbackamplifier.Therefore,it is capable of realizing high speed and high precision.For improving theperformance and producibility,the tolerance extension,design centering and potential adaptingtechniques are used in the design of comparator ZJ03. 展开更多
关键词 Voltage comparator Latching voltage comparator Tolerance extension Potential adapting
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A Novel Power Optimization Method by Minimum Comparator Number Algorithm for Pipeline ADCs 认领 引用 被引量：1
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作者 宁宁 吴霜毅 +1 位作者 王向展 杨谟华 《Journal of Electronic Science and Technology of China》 2007年第1期75-80,共6页
The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator ... The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator number algorithm （MCNA） is first introduced, and then the optimum distribution of resolutions through pipeline ADC stages is deduced by MCNA. Based on the optimum stage-resolution distribution, an optimization method is established, which examines the precise function between ADC power and stage resolutions with a parameter of power ratio （Rp）. For 10-bit pipeline ADC with scaling down technology, the simulation results by using MATLAB CAD tools show that an eight-stage topology with 1-bit RSD correction achieves the power optimization indicated by the power reduction ratio. 展开更多
关键词 minimum comparator number algorithm pipeline analog-to-digital converter ,power dissipation scaling down stage resolution
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Brief introduction for search and determination of the comparator product for generic medicinal product application in the EU 认领 引用
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作者 Jianzhao Niu Dongsheng Yang Mingdi Xu 《Journal of Chinese Pharmaceutical Sciences》 CAS CSCD 2018年第11期805-812,共8页
It is vital segment to choose the right comparator product during the development and study of generic medicinal product, and this is also definitely specified in the relevant documents from the China Food and Drug Ad... It is vital segment to choose the right comparator product during the development and study of generic medicinal product, and this is also definitely specified in the relevant documents from the China Food and Drug Administration (CFDA)that the comparator product should be innovator product or internationally recognized same medicinal product,which is used in the re-evaluation of generic medicinal product or marketed authorization application of the generic medicinal product.To facilitate the domestic and foreign pharmaceutical enterprises to choose and determine comparator product,four medicinal product evaluation procedures,as well as the corresponding marketed medicinal product list,are detailed elaborated in this paper.At the same time, by taking the Mifepristone Tablet (200mg)as example,the search and determination process of the comparator product for generic medicinal product application in the EU is illustrated with the combination of different marketed medicinal product lists. 展开更多
关键词 Comparator product Re-evaluation of generic medicinal product Marketing authorization application Mifepristone tablet
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A Time-Domain Comparator Based Skipping-Window SAR ADC 认领 引用 被引量：1
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作者 Liangbo Xie Yan Ren +2 位作者 Mu Zhou Xiaolong Yang Zhengwen Huang 《Computers, Materials & Continua》 SCIE EI 2021年第11期1597-1609,共13页
This paper presents an energy efficient successive-approximation register(SAR)analog-to-digital converter(ADC)for low-power applications.To improve the overall energy-efficiency,a skipping-window technique is used to ... This paper presents an energy efficient successive-approximation register(SAR)analog-to-digital converter(ADC)for low-power applications.To improve the overall energy-efficiency,a skipping-window technique is used to bypass corresponding conversion steps when the input falls in a window indicated by a time-domain comparator,which can provide not only the polarity of the input,but also the amount information of the input.The timedomain comparator,which is based on the edge pursing principle,consists of delay cells,two NAND gates,two D-flip-flop register-based phase detectors and a counter.The digital characteristic of the comparator makes the design more flexible,and the comparator can achieve noise and power optimization automatically by simply adjusting the delay cell number.An energy efficient digital-to-analog converter(DAC)control scheme suitable for the skipping window technique is also developed to reduce the switching energy during SAR conversion.Together with the skipping-window technique,the linearity and the power consumption of the SAR ADC are improved.The impact of different window sizes on comparison cycles,DAC switching energy and the overall energy efficiency is analyzed.Simulation results show that the proposed skipping-window technique can improve the overall energy-efficiency of the SAR ADC,as well as the linearity,and the optimized window size for the overall energy efficiency will vary with the DAC switching energy. 展开更多
关键词 Skipping-window technique DAC switching scheme timedomain comparator low-power
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Trinary magnitude comparator using SLM based Savart plate 认领 引用 被引量：1
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作者 Animesh Bhattacharya Shyandeep Das +2 位作者 Arijit Sarkar Nabanita Bose Amal K Ghosh 《Optoelectronics Letters》 EI 2019年第6期415-419,共5页
The demand of present technology inviting the popularity of multivalued optical computation system to coup up with the latest scenario of ultrahigh processing speed and handling large amount of data The magnitude comp... The demand of present technology inviting the popularity of multivalued optical computation system to coup up with the latest scenario of ultrahigh processing speed and handling large amount of data The magnitude comparator is the heart of the arithmetic and logic unit(ALU)in any logical processing and computing system.In this paper,a trinary magnitude comparator circuit has been proposed and implemented with modified trinary number(MTN)system.Optical tree architecture(OTA)of the proposed circuit has been realized reasonably using Savart plate and spatial light modulators(SLM).A simulation algorithm has also been developed and implemented to prove the authenticity of the proposed circuit through the simulation. 展开更多
关键词 comparator system. magnitude
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A CMOS Dynamic Comparator for Pipelined ADCs with Improved Speed/Power Ratio 认领 引用 被引量：8
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作者 刘珂 杨海钢 《Journal of Semiconductors》 CAS 北大核心 2008年第1期75-81,共7页
This paper presents a fully-differential CMOS dynamic comparator for use in high-speed pipelined ADCs with low stage resolution. Because the architecture is based on the coupled current sources and differential input ... This paper presents a fully-differential CMOS dynamic comparator for use in high-speed pipelined ADCs with low stage resolution. Because the architecture is based on the coupled current sources and differential input pairs, this comparator＇s threshold voltage can be adjusted to a desired level. Compared with traditional comparators, this one shows significant improvement in area,power,and speed. Fabricated in 0.35μm CMOS technology,it occupies only 30μm × 70μm. Simulation and measurement results indicate the comparator has a sampling frequency up to 1GHz with 2Vpp differential input signal range and only 181μW power consumption under a 3.3V supply. The speed/power ratio reaches up to 5524GS/J. 展开更多
关键词 CMOS comparator ADC
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Single-Bit Comparator in Quantum-Dot Cellular Automata (QCA) Technology Using Novel QCAXNOR Gates 认领 引用
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作者 Ali Hussien Majeed Mohd Shamian Zainal +1 位作者 Esam Alkaldy Danial Md.NorNor 《Journal of Electronic Science and Technology》 EI CAS CSCD 2021年第3期263-273,共11页
To fill the continuous needs for faster processing elements with less power consumption causes large pressure on the complementary metal oxide semiconductor(CMOS)technology developers.The scaling scenario is not an op... To fill the continuous needs for faster processing elements with less power consumption causes large pressure on the complementary metal oxide semiconductor(CMOS)technology developers.The scaling scenario is not an option nowadays and other technologies need to be investigated.The quantum-dot cellular automata(QCA)technology is one of the important emerging nanotechnologies that have attracted much researchers’attention in recent years.This technology has many interesting features,such as high speed,low power consumption,and small size.These features make it an appropriate alternative to the CMOS technique.This paper suggests three novel structures of XNOR gates in the QCA technology.The presented structures do not follow the conventional approaches to the logic gates design but depend on the inherent capabilities of the new technology.The proposed structures are used as the main building blocks for a single-bit comparator.The resulted circuits are simulated for the verification purpose and then compared with existing counterparts in the literature.The comparison results are encouraging to append the proposed structures to the library of QCA gates. 展开更多
关键词 Nanotechnology quantum-dot cellular automata(QCA) QCA comparator XNOR gate XOR gate
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A Two-Dimension Time-Domain Comparator for Low Power SAR ADCs 认领 引用
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作者 Liangbo Xie Sheng Li +1 位作者 Yan Ren Zhengwen Huang 《Computers, Materials & Continua》 SCIE EI 2020年第11期1519-1529,共11页
This paper presents a two-dimension time-domain comparator suitable for low power successive-approximation register(SAR)analog-to-digital converters(ADCs).The proposed two-dimension time-domain comparator consists of ... This paper presents a two-dimension time-domain comparator suitable for low power successive-approximation register(SAR)analog-to-digital converters(ADCs).The proposed two-dimension time-domain comparator consists of a ring oscillator collapse-based comparator and a counter.The propagation delay of a voltage controlled ring oscillator depends on the input.Thus,the comparator can automatically change the comparison time according to its input difference,which can adjust the power consumption of the comparator dynamically without any control logic.And a counter is utilized to count the cycle needed to finish a comparison when the input difference is small.Thus,the proposed comparator can not only provide the polarity of the input,but also the amount information of the input,which helps to skip most of the SAR cycles when the initial input is small.Thus,most energy can be saved when the initial input is small.The proposed time-domain comparator is designed in 0.18μm CMOS technology.Simulation results demonstrate that the comparator can not only save power consumption,but also give the design flexibility,and the current is only nA level when the supply voltage is 0.6 V. 展开更多
关键词 Time-domain comparator two dimensions low power
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Design of Low Power Comparator Using DG Gate 认领 引用
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作者 Bahram Dehghan Abdolreza Roozbeh Jafar Zare 《Circuits and Systems》 2014年第1期7-12,共6页
In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as ... In recent studies, reversible logic has emerged as a great scene of research, having applications in low power CMOS circuits, optical computing, quantum computing and nanotechnology. The classical logic gates such as AND, OR, EXOR and EXNOR are not reversible. In the existing literature, reversible sequential circuits designs are offered that are improved for the number of the garbage outputs and reversible gates. Minimizing the number of garbage is very noticeable. In the present paper, we show a design of the reversible comparator based on the quantum gates implementation of the reversible DG gate. The reversible DG gate is designed by using 3 × 3 quantum gates such as NOT, CNOT, Controlled-V and Controlled-V+ gates. Also, we have used the TR gate and various types of quantum gates in the implementation results. Low power three-bit comparator is designed using DG Gate, New Gate and Fredkin Gate. In order to evaluate the benefit of using the DG gate proposed in this paper, one-bit comparator is constructed. The design is useful for the future computing techniques like quantum computers. The proposed designs are implemented using VHDL and functionally investigated using Quartus II simulator. 展开更多
关键词 Reversible Logic Comparator TR and DG Gate Quantum Cost Garbage Output
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A 0.5-V, 1.2-GS/s, 6-Bit Flash ADC Using Temporarily-Boosted Comparator 认领 引用
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作者 Kenichi Ohhata Masataro Iwamoto Naoto Yamaguchi 《Circuits and Systems》 2015年第8期179-187,共9页
A low-voltage, high-speed flash ADC is designed. The bottleneck of the operation speed in the low-voltage region is the delay time increase of the comparator. The temporarily boosted comparator is proposed to address ... A low-voltage, high-speed flash ADC is designed. The bottleneck of the operation speed in the low-voltage region is the delay time increase of the comparator. The temporarily boosted comparator is proposed to address this problem. The proposed circuit only boosts the supply voltage in the comparison phase, and therefore, can reduce the delay time while keeping the power overhead to a minimum. Moreover, the body bias control calibration is combined with the temporarily boosted technique. This helps to create a low-power and high-precision comparator. A 0.5-V, 6-bit flash ADC was designed by using 65-nm CMOS technology to demonstrate the effectiveness of the proposed technique. The simulation results showed a high sampling frequency of 1.2 GHz, a low power consumption of 1.4 mW, and an FOM of 28 fJ/conv.-step even at a low supply voltage of 0.5 V. 展开更多
关键词 ADC Low Voltage Flash Comparator Calibration
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Analysis on the Magnetic Shielding Effectiveness of DC Current Comparator 认领 引用
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作者 Jiayun Song Pan Pan +2 位作者 Qizheng Ji Shuqiang Wang Biye Liu 《Journal of Applied Mathematics and Physics》 2016年第2期478-486,共9页
There are magnetic interference problems in the applications of DC current comparator. Analysis on the magnetic effectiveness which is applied by the external magnetic field is introduced in this paper. The effectiven... There are magnetic interference problems in the applications of DC current comparator. Analysis on the magnetic effectiveness which is applied by the external magnetic field is introduced in this paper. The effectiveness is proved by the actual results which are compared with the magnetic- circuit method and the finite element method. In addition, the reference comment is given which can be used in the practical work of DC current comparator shield design. 展开更多
关键词 Magnetic Shielding Effectiveness DC Current Comparator the Magnetic-Circuit Method the Finite Element Method
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A 20-GHz ultra-high-speed InP DHBT comparator 认领 引用 被引量：2
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作者 黄振兴 周磊 +1 位作者 苏永波 金智 《Journal of Semiconductors》 EI CAS CSCD 2012年第7期80-84,共5页
An ultra-high-speed, master-slave voltage comparator circuit is designed and fabricated using InP/GaInAs double heterojunction bipolar transistor technology with a current gain cutoff frequency of 170 GHz. The complet... An ultra-high-speed, master-slave voltage comparator circuit is designed and fabricated using InP/GaInAs double heterojunction bipolar transistor technology with a current gain cutoff frequency of 170 GHz. The complete chip die, including bondpads, is 0.75 × 1.04 mm22. It consumes 440 mW from a single M V power supply, excluding the clock part. 77 DHBTs have been used in the monolithic comparator. A full Nyquist test has been performed up to 20 GHz, with the input sensitivity varying from 6 mV at l0 GHz to 16 mV at 20 GHz. To our knowledge, this is the first InP based integrated circuit including more than 70 DHBTs, and it achieves the highest sampling rate found on the mainland of China. 展开更多
关键词 InP comparator HBT emitter coupled logic latched comparator sensitivity
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A SHA-less 14-bit,100-MS/s pipelined ADC with comparator offset cancellation in background 认领 引用 被引量：2
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作者 Wang Xiaofei Zhang Hong +2 位作者 Zhang Jie Du Xin Hao Yue 《Journal of Semiconductors》 EI CAS CSCD 2016年第3期81-87,共7页
A 14-bit 100-MS/s pipelined analog-to-digital converter(ADC)without dedicated front-end sampleand-hold amplifier(SHA)is presented.In addition to elaborate matching of the sampling network in the first stage,a backgrou... A 14-bit 100-MS/s pipelined analog-to-digital converter(ADC)without dedicated front-end sampleand-hold amplifier(SHA)is presented.In addition to elaborate matching of the sampling network in the first stage,a background offset cancellation circuit is proposed in this paper to suppress the offset of the comparators in the first-stage sub-ADC,which ensures the overall offset does not exceed the correction range of the built-in redundant structure.Fabricated in a 0.18-m CMOS technology,the presented ADC occupies a chip area of 12 mm2,and consumes 237 mW from a 1.8-V power supply.Measurement results with a 30.1-MHz input sine wave under a sampling rate of 100 MS/s show that the ADC achieves a 71-d B signal-to-noise and distortion ratio(SNDR),an 85.4-d B spurious-free dynamic range(SFDR),a maximum differential nonlinearity(DNL)of 0.22 LSB and a maximum integral nonlinearity(INL)of 1.4 LSB. 展开更多
关键词 SHA-less pipelined ADC clock skew comparator offset background
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A high speed low power low offset dynamic comparator used in SHA-less pipelined ADC 认领 引用 被引量：2
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作者 刘术彬 朱樟明 +1 位作者 杨银堂 刘帘曦 《Journal of Semiconductors》 EI CAS CSCD 2014年第5期110-117,共8页
A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier （SHA）-less pipelined analog-to-digital ... A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier （SHA）-less pipelined analog-to-digital converters （ADC）. Based on the analysis and optimization between delay time and offset, an enhanced reset architecture with transmission gate was introduced to speed up the comparison and reset procedure. Four inputs with two cross coupled differential pairs, reconstituted bias circuit for tail current transistor and common centroid layouts make the comparator more robust against mismatch and process variations. The simulation results demonstrate that the proposed design achieves 1 mV sensitivity at 2.2 GHz sampling rate with a power consumption of 510 μW, while the mean offset voltage is equal to 10.244 mV. 展开更多
关键词 SHA-less ADC dynamic comparator high speed low offset low power transmission gate
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A low power 20 GHz comparator in 90 nm COMS technology 认领 引用 被引量：2
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作者 唐凯 孟桥 +1 位作者 王志功 郭婷 《Journal of Semiconductors》 EI CAS CSCD 2014年第5期74-79,共6页
A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters （ADCs） is proposed. The time constant in both the tracking and regeneration phases of the ... A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters （ADCs） is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic （SCL） topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65 × 150 μm^2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second （GSps） with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications. 展开更多
关键词 comparator ADC ultra-high-speed low power latch CMOS
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A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator 认领 引用 被引量：8
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作者 杨思宇 张辉 +2 位作者 付文汇 易婷 洪志良 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2011年第3期88-93,共6页
A low power 12-bit 200-kS/s SAR ADC is proposed.This features a differential time domain comparator whose offset is cancelled by using a charge pump and a phase frequency detector instead of the preamplifiers usually ... A low power 12-bit 200-kS/s SAR ADC is proposed.This features a differential time domain comparator whose offset is cancelled by using a charge pump and a phase frequency detector instead of the preamplifiers usually needed in a high resolution comparator.The proposed ADC is manufactured in 0.18-μm CMOS technology and the measured SNR and SNDR are 62.5 dB and 59.3 dB,respectively,with a power consumption of 72μW at a 200-kS/s sampling rate.The device operates with a 1.8-V power supply and achieves a FOM of 477 fJ/conversion-step. 展开更多
关键词 successive approximation register A/D differential time domain comparator
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An offset cancellation technique in a switched-capacitor comparator for SAR ADCs 认领 引用 被引量：2
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作者 Tong Xingyuan Zhu Zhangming Yang Yintang 《Journal of Semiconductors》 EI CAS CSCD 2012年第1期144-148,共5页
An offset cancellation technique for a SAR （successive approximation register） ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and... An offset cancellation technique for a SAR （successive approximation register） ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and realized in 0.18μm CMOS. With the first stage preamplifier offset cancellation and low offset regenerative latching approach, the equivalent offset of the comparator is reduced to 〈 0.55 mV. By using the pre-amplifying and regenerative latching comparison mode the comparator exhibits low power dissipation. Under a 1.8 V power supply, with a 200 kS/s ADC sampling rate and 3 MHz clock frequency, a 13-bit comparison resolution is reached and less than 0.09 mW power dissipation is consumed. The superiority of this comparator is discussed and proved by the post-simulation and application to a 10 bit 200 kS/s touch screen SAR A/D converter. 展开更多
关键词 A/D converter switched-capacitor comparator preamplifier regenerative latch low power low off-set
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Effect of a reset-MOSFET in a high-speed comparator 认领 引用 被引量：1
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作者 刘海涛 孟桥 +1 位作者 王志功 唐凯 《Journal of Semiconductors》 EI CAS 北大核心 2009年第7期86-90,共5页
A high-speed comparator design based on regeneration architecture, which can be used in a flash ADC, is presented.A threshold-limit-speed effect（TLSE） which limits the speed of the comparator was discovered and stud... A high-speed comparator design based on regeneration architecture, which can be used in a flash ADC, is presented.A threshold-limit-speed effect（TLSE） which limits the speed of the comparator was discovered and studied in detail.The size of the reset-MOSFET was optimized to resolve the TLSE and make the comparator work at the maximal speed.The results were confirmed by simulation and the corresponding circuit was realized in a flash ADC design in SMIC 0.18-μm CMOS technology.The test result shows that the comparator can work well at 2 GHz and can even work up to 2.8 GHz while the power dissipation is 3.2 mW. 展开更多
关键词 comparator high speed TLSE CMOS ADC
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