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A Fast Half-Pixel Motion Estimation Algorithm and Efficient Interpolation Hardware Architecture Unit for H.264/AVC 认领 引用
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作者 Zuo Chunsheng Lin Tao Fan Jing 《International Journal of Technology Management》 2015年第1期73-76,共4页
In this paper, a fast half-pixel motion estimation algorithm and its corresponding hardware architecture is presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented alg... In this paper, a fast half-pixel motion estimation algorithm and its corresponding hardware architecture is presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs only two steps to obtain all the interpolated pixels of an entire 8x8 block. The proposed architecture works in a parallel way and is simulated by Modelsirn 6.5 SE, synthesized to the Xilinx Virtex4 XC4VLX15 FPGA device. The implementation results show that this architecture can achieve 190 MHz and 10 clock cycles are reduced to complete the entire interpolation process when compared with typical half-pixel interpolation, which meets the requirements of real-time application for very high defination videos. 展开更多
关键词 Motion estimation Half-pixel interpolation Hardware architecture FPGA
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A cascadable stereo matching processor with pixel-wise fusion for extended depth sensing 认领 引用 被引量：1
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作者 Zhuoyu Chen Pingcheng Dong +4 位作者 Zhiyong Lai Wenyue Zhang Xianglong Wang Lei Chen Fengwei An 《Journal of Semiconductors》 EI CAS CSCD 2026年第6期59-71,共13页
Achieving long-range,high-accuracy depth perception under stringent power constraints remains a critical challenge for stereo vision in edge applications.This work presents a cascadable stereo matching processor that ... Achieving long-range,high-accuracy depth perception under stringent power constraints remains a critical challenge for stereo vision in edge applications.This work presents a cascadable stereo matching processor that overcomes the inherent trade-off between sensing range and computational efficiency.The core innovation is a scalable semi-global matching(SSGM)algorithm which dynamically optimizes the disparity search range for different baselines,ensuring constant on-chip memory usage and a significant reduction in data movement.The architecture further integrates a raw-domain rectification front-end,which performs direct geometric transformation on Bayer-patterned image streams.This approach eliminates the need for external memory access by bypassing conventional ISP pipelines,thereby maximizing throughput and reducing system memory consumption.Parallel processing paths for multiple baselines converge in a pixel-wise fusion module,which synthesizes a unified depth map by selecting the most reliable disparity estimate for each output pixel.The cascadable stereo matching processor achieves speedups of up to 178x and 97x over CPU and EdgeGPU platforms,respectively,in multi-baseline stereo disparity fusion.Implemented in 40-nm CMOS technology,the processor operates at 160 MHz,achieving a processing speed of 80 frames per second with an energy efficiency of 7.9 pJ/pixel and occupying a core area of 6.04 mm2. 展开更多
关键词 hardware architecture stereo vision real-time system multi-baseline stereo disparity fusion
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Analysis of Hardware and Software Safety Architecture of Dual Motor Controller System in Hybrid Electric Vehicles 认领 引用
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作者 MA Tianyu LI Zhuangzhuang +3 位作者 YAN Bowen LIU Bin DENG Wei ZHANG Xiaoyu 《同济大学学报（自然科学版）》 EI CAS CSCD 北大核心 2025年第S1期26-39,共14页
The dual-motor controller system is one of the key components in the multi-power architecture of new energy vehicles and is crucial to the safe operation of the vehicle.From the perspective of functional safety,this a... The dual-motor controller system is one of the key components in the multi-power architecture of new energy vehicles and is crucial to the safe operation of the vehicle.From the perspective of functional safety,this article takes the torque safety goal of"avoiding unexpected acceleration of the vehicle due to unexpected acceleration torque"as an example to explore various software and hardware architecture implementation methods,and analysis the test scheme covering multiple stages such as HIL/PowerHIL testing,bench testing and vehicle testing to verify the effectiveness of the safety path.Through the verification of the safety strategy,it provides innovative ideas for the functional safety design and testing of the electric drive control system,which is expected to provide a reference for improving the overall safety of new energy vehicles. 展开更多
关键词 new energy vehicles motor control unit functional safety software and hardware architecture
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Study of An Integrated Security Solution for Network Information System 认领 引用
4
作者 Yangqing Zhu 《通讯和计算机（中英文版）》 2006年第3期35-39,56,共5页
The Internet-based network information system brings a series of security problems, such as the ability of fault tolerance, the ability of disaster tolerance, the ability of secret communication, secret data storage, ... The Internet-based network information system brings a series of security problems, such as the ability of fault tolerance, the ability of disaster tolerance, the ability of secret communication, secret data storage, clients＇ authentication and so on. In this paper, we study the integrated security of network information system from hardware architecture, data encryption, authentication, firewall and application. 展开更多
关键词 Network Information System Hardware Architecture Data Encryption Authentication Firewall Application Security
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Microcomb-enabled parallel self-calibration optical convolution streaming processor 认领 引用
5
作者 Jiajia Wang Xingyuan Xu +13 位作者 Xiaotian Zhu Yifu Xu Shifan Chen Haoran Zhang Yixuan Zheng Shuying Li Yunping Bai Zhihui Liu Roberto Morandotti Brent E.Little Sai T.Chu Arthur J.Lowery David J.Moss Kun Xu 《Light: Science & Applications》 SCIE EI CAS CSCD 2026年第5期1606-1616,共11页
The exponential growth of cloud computing and artificial intelligence(AI)applications has driven an urgent need for high-bandwidth,energy-efficient hardware architectures in data centers.With Moore’s Law nearing its ... The exponential growth of cloud computing and artificial intelligence(AI)applications has driven an urgent need for high-bandwidth,energy-efficient hardware architectures in data centers.With Moore’s Law nearing its limits,optical neuromorphic computing hardware offers a promising alternative,providing ultra-high speeds and minimal energy consumption due to its analog architecture.Here,we propose the microcomb-enabled parallel optical convolution streaming processor(OCSP)with time,space,and wavelength three-dimensional multiplexing,operating at data rates of 50 GBaud or higher,achieving a convolution computing speed of up to 4 trillion operations per second(TOPS).Moreover,the OCSP uses a robust self-calibration mechanism to achieve accurate optical phase calibration and set-up of its convolution function.This innovative approach leverages time-space interleaving passive periodic interference architecture,incorporating wavelength-division-multiplexing technology,and is verified experimentally for parallel image feature extraction and recognition tasks.Our OCSP offers a practical pathway for seamlessly integrating photonic computing units into data center interconnects,unlocking photonic computing’s potential for scalable,lowlatency AI workloads. 展开更多
关键词 data centerswith analog architectureherewe artificial intelligence ai applications optical neuromorphic computing optical convolution streaming processor ocsp cloud computing neuromorphic computing hardware hardware architectures
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Reconfigurable intelligent surfaces for wireless communications:Overview of hardware designs,channel models,and estimation techniques 认领 引用 被引量：21
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作者 Mengnan Jian George C.Alexandropoulos +4 位作者 Ertugrul Basar Chongwen Huang Ruiqi Liu Yuanwei Liu Chau Yuen 《Intelligent and Converged Networks》 EI 2022年第1期1-32,共32页
The demanding objectives for the future sixth generation(6G)of wireless communication networks have spurred recent research efforts on novel materials and radio-frequency front-end architectures for wireless connectiv... The demanding objectives for the future sixth generation(6G)of wireless communication networks have spurred recent research efforts on novel materials and radio-frequency front-end architectures for wireless connectivity,as well as revolutionary communication and computing paradigms.Among the pioneering candidate technologies for 6G belong the reconfigurable intelligent surfaces(RISs),which are artificial planar structures with integrated electronic circuits that can be programmed to manipulate the incoming electromagnetic field in a wide variety of functionalities.Incorporating RISs in wireless networks have been recently advocated as a revolutionary means to transform any wireless signal propagation environment to a dynamically programmable one,intended for various networking objectives,such as coverage extension and capacity boosting,spatiotemporal focusing with benefits in energy efficiency and secrecy,and low electromagnetic field exposure.Motivated by the recent increasing interests in the field of RISs and the consequent pioneering concept of the RIS-enabled smart wireless environments,in this paper,we overview and taxonomize the latest advances in RIS hardware architectures as well as the most recent developments in the modeling of RIS unit elements and RIS-empowered wireless signal propagation.We also present a thorough overview of the channel estimation approaches for RIS-empowered communications systems,which constitute a prerequisite step for the optimized incorporation of RISs in future wireless networks.Finally,we discuss the relevance of the RIS technology in the latest wireless communication standards,and highlight the current and future standardization activities for the RIS technology and the consequent RIS-empowered wireless networking approaches. 展开更多
关键词 reconfigurable intelligent surfaces beyond 5G 6G channel modeling hardware architecture channel estimation smart wireless environment standardization
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