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Hybridization of Metaheuristics Based Energy Efficient Scheduling Algorithm for Multi-Core Systems 认领 引用
1
作者 J.Jean Justus U.Sakthi +4 位作者 K.Priyadarshini B.Thiyaneswaran Masoud Alajmi Marwa Obayya Manar Ahmed Hamza 《Computer Systems Science & Engineering》 SCIE EI 2023年第1期205-219,共15页
The developments of multi-core systems(MCS)have considerably improved the existing technologies in thefield of computer architecture.The MCS comprises several processors that are heterogeneous for resource capacities,... The developments of multi-core systems(MCS)have considerably improved the existing technologies in thefield of computer architecture.The MCS comprises several processors that are heterogeneous for resource capacities,working environments,topologies,and so on.The existing multi-core technology unlocks additional research opportunities for energy minimization by the use of effective task scheduling.At the same time,the task scheduling process is yet to be explored in the multi-core systems.This paper presents a new hybrid genetic algorithm(GA)with a krill herd(KH)based energy-efficient scheduling techni-que for multi-core systems(GAKH-SMCS).The goal of the GAKH-SMCS tech-nique is to derive scheduling tasks in such a way to achieve faster completion time and minimum energy dissipation.The GAKH-SMCS model involves a multi-objectivefitness function using four parameters such as makespan,processor utilization,speedup,and energy consumption to schedule tasks proficiently.The performance of the GAKH-SMCS model has been validated against two datasets namely random dataset and benchmark dataset.The experimental outcome ensured the effectiveness of the GAKH-SMCS model interms of makespan,pro-cessor utilization,speedup,and energy consumption.The overall simulation results depicted that the presented GAKH-SMCS model achieves energy effi-ciency by optimal task scheduling process in MCS. 展开更多
关键词 Task scheduling energy efficiency multi-core systems fitness function makespan
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Design and optimization of weakly coupled multi-core fiber 认领 引用
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作者 ZHAN Yi WANG An +1 位作者 ZHANG Qing-long WANG Yi-han 《中国光学（中英文）》 EI CAS CSCD 北大核心 2026年第3期730-744,共15页
In order to achieve comprehensive,highly efficient,and multi-objective precise optimization of fiber structural parameters and further enhance the transmission capacity of optical communication systems,a homogeneous w... In order to achieve comprehensive,highly efficient,and multi-objective precise optimization of fiber structural parameters and further enhance the transmission capacity of optical communication systems,a homogeneous weakly coupled seven-core fiber based on trench-assisted structures is designed.Particle Swarm Optimization(PSO)is introduced to replace traditional empirical designs or local scanning methods.First,a multi-objective fitness function incorporating constraints such as dispersion,cutoff wavelength,ef-fective mode field area,and coating loss is established.Then,the algorithm performs a global search to pre-cisely determine the optimal structural parameters under standard dimensional constraints.Simulation results demonstrate that with a fiber core pitch of 45μm,the optimized fiber achieves an ultra-low inter-core crosstalk of below−90 dB/km at a wavelength of 1550 nm.This design scheme not only effectively resolves the conflict between crosstalk suppression and spatial utilization in multi-core fibers but also proves the effi-ciency and reliability of the PSO algorithm in complex fiber structural design,providing an important theor-etical basis and technical support for the research and manufacturing of ultra-large-capacity optical commu-nication systems. 展开更多
关键词 multi-core fiber particle swarm optimization trench-assisted inter-core crosstalk space divi-sion multiplexing
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Heterogeneous multi-core task scheduling based on adaptive simulated annealing 认领 引用
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作者 ZHU Guoliang ZHANG Jinjian +4 位作者 LIU Xuan WANG Guojun ZHANG Xiaodong CHEN Kaiyu WANG Yu 《Journal of Systems Engineering and Electronics》 SCIE CSCD 2026年第3期897-903,共7页
To address the energy consumption issues caused by task lengths in task scheduling on heterogeneous multi-core systems,this paper proposes an adaptive parameterized improved simulated annealing algorithm based on the ... To address the energy consumption issues caused by task lengths in task scheduling on heterogeneous multi-core systems,this paper proposes an adaptive parameterized improved simulated annealing algorithm based on the directed acyclic graph task model.The algorithm employs feedback from acceptance rates to dynamically adjust the temperature and neighborhood size of the simulated annealing process.Additionally,it introduces a security mechanism to enhance convergence speed and global search capabilities.Compared against classical simulated annealing and standard heuristic algorithms,the proposed algorithm achieves reductions exceeding 54% in convergence generations,50% in task slots,and 10% in scheduling time,providing a direction for low-power task scheduling. 展开更多
关键词 heterogeneous multi-core task scheduling schedule length simulated annealing
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Preparation and sustained release performance of multi-core capsules based on fragrance-loaded Pickering emulsions 认领 引用
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作者 Xinyi Liu Juanbo Chen +4 位作者 Haoyue Hou Jiawei Hou Meiling Shi Sa Zeng Tao Meng 《日用化学工业（中英文）》 CAS 北大核心 2025年第3期286-294,共9页
Naturally degradable capsule provides a platform for sustained fragrance release.However,practical challenges such as low encapsulation efficiency and difficulty in sustained release are still limited in using fragran... Naturally degradable capsule provides a platform for sustained fragrance release.However,practical challenges such as low encapsulation efficiency and difficulty in sustained release are still limited in using fragranceloaded capsules.In this work,the natural materials sodium alginate and gelatine are dissolved and act as the aqueous phase,lavender is dissolved in caprylic/capric triglyceride(GTCC)as the oil phase,and SiO2 nanoparticles with neutralwettability as a solid emulsifier to form O/W Pickering emulsions simultaneously.Finally,multi-core capsules are prepared using the drop injection method with emulsions as templates.The results show that the capsules have been successfully prepared with a spherical morphology and multi-core structure,and the encapsulation rate of multi-core capsules can reach up to 99.6%.In addition,the multi-core capsules possess desirable sustained release performance,the cumulative sustained release rate of fragrance at 25℃over 49 days is only 32.5%.It is attributed to the significant protection of multi-core structure,Pickering emulsion nanoparticle membranes,and hydrogel network shell for encapsulated fragrance.This study is designed to deliver a new strategy for using sustained-release technology with fragrance in food,cosmetics,textiles,and other fields. 展开更多
关键词 fragrance Pickering emulsion multi-core capsules encapsulation efficiency sustained release
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Parallel scheduling strategy of web-based spatial computing tasks in multi-core environment 认领 引用
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作者 郭明强 Huang Ying Xie Zhong 《High Technology Letters》 EI CAS 2014年第4期395-400,共6页
In order to improve the concurrent access performance of the web-based spatial computing system in cluster,a parallel scheduling strategy based on the multi-core environment is proposed,which includes two levels of pa... In order to improve the concurrent access performance of the web-based spatial computing system in cluster,a parallel scheduling strategy based on the multi-core environment is proposed,which includes two levels of parallel processing mechanisms.One is that it can evenly allocate tasks to each server node in the cluster and the other is that it can implement the load balancing inside a server node.Based on the strategy,a new web-based spatial computing model is designed in this paper,in which,a task response ratio calculation method,a request queue buffer mechanism and a thread scheduling strategy are focused on.Experimental results show that the new model can fully use the multi-core computing advantage of each server node in the concurrent access environment and improve the average hits per second,average I/O Hits,CPU utilization and throughput.Using speed-up ratio to analyze the traditional model and the new one,the result shows that the new model has the best performance.The performance of the multi-core server nodes in the cluster is optimized;the resource utilization and the parallel processing capabilities are enhanced.The more CPU cores you have,the higher parallel processing capabilities will be obtained. 展开更多
关键词 parallel scheduling strategy the web-based spatial computing model multi-core environment load balancing
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Multi-core optimization for conjugate gradient benchmark on heterogeneous processors 认领 引用
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作者 邓林 窦勇 《Journal of Central South University》 SCIE EI CAS 2011年第2期490-498,共9页
Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at t... Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at this problem,a parallelization approach was proposed with six memory optimization schemes for CG,four schemes of them aiming at all kinds of sparse matrix-vector multiplication (SPMV) operation. Conducted on IBM QS20,the parallelization approach can reach up to 21 and 133 times speedups with size A and B,respectively,compared with single power processor element. Finally,the conclusion is drawn that the peak bandwidth of memory access on Cell BE can be obtained in SPMV,simple computation is more efficient on heterogeneous processors and loop-unrolling can hide local storage access latency while executing scalar operation on SIMD cores. 展开更多
关键词 multi-core processor NAS parallelization CG memory optimization
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RF-TSV DESIGN, MODELING AND APPLICATION FOR 3D MULTI-CORE COMPUTER SYSTEMS 认领 引用
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作者 Yu Le Yang Haigang Xie Yuanlu 《Journal of Electronics(China)》 2012年第5期431-444,共14页
The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient... The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs. 展开更多
关键词 Three Dimensional (3D) Very Large Scale Integrated circuits (VLSI) Ratio Frequency (RF) Through-Silicon Vias (TSVs) Multi-core computer technology
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Enrichment of Fetal Nucleated Red Blood Cells by Multi-core Magnetic Composite Particles for Non-invasive Prenatal Diagnosis 认领 引用 被引量：1
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作者 PAN Ying WANG Qing +7 位作者 HUANG Wen-jun QIAO Feng-1i LIU Yu-ping ZHANG Yu-cheng HAI De-yang DU Ying,ting WANG Wen-yue ZHANG Ai-chen 《Chemical Research in Chinese Universities》 SCIE CAS CSCD 2012年第3期443-448,共6页
A novel kind of multi-core magnetic composite particles, the surfaces of which were respectively mo- dified with goat-anti-mouse IgG and antitransferrin receptor（anti-CD71）, was prepared. The fetal nucleated red blo... A novel kind of multi-core magnetic composite particles, the surfaces of which were respectively mo- dified with goat-anti-mouse IgG and antitransferrin receptor（anti-CD71）, was prepared. The fetal nucleated red blood cells（FNRBCs） in the peripheral blood of a gravida were rapidly and effectively enriched and separated by the mo- dified multi-core magnetic composite particles in an external magnetic field. The obtained FNRBCs were used for the identification of the fetal sex by means of fluorescence in situ hybridization（FISH） technique. The results demonstrate that the multi-core magnetic composite particles meet the requirements for the enrichment and speration of FNRBCs with a low concentration and the accuracy of detetion for the diagnosis of fetal sex reached to 95%. Moreover, the obtained FNRBCs were applied to the non-invasive diagnosis of Down syndrome and chromosome 3p21 was de- tected. The above facts indicate that the novel multi-core magnetic composite particles-based method is simple, relia- ble and cost-effective and has opened up vast vistas for the potential application in clinic non-invasive prenatal diag- nosis. 展开更多
关键词 Fetal nucleated red blood cell（FNRBC） Prenatal diagnosis Non-invasive Multi-core magnetic compositeparticle
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Optimizing Multi-Dimensional Packet Classification for Multi-Core Systems 认领 引用 被引量：1
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作者 Tong Shen Da-Fang Zhang +1 位作者 Gao-Gang Xie Xin-Yi Zhang 《Journal of Computer Science & Technology》 SCIE EI CSCD 2018年第5期1056-1071,共16页
Packet classification has been studied for decades; it classifies packets into specific flows based on a given rule set. As software-defined network was proposed, a recent trend of packet classification is to scale th... Packet classification has been studied for decades; it classifies packets into specific flows based on a given rule set. As software-defined network was proposed, a recent trend of packet classification is to scale the five-tuple model to multi-tuple. In general, packet classification on multiple fields is a complex problem. Although most existing software-based algorithms have been proved extraordinary in practice, they are only suitable for the classic five-tuple model and difficult to be scaled up. Meanwhile, hardware-specific solutions are inflexible and expensive, and some of them are power consuming. In this paper, we propose a universal multi-dimensional packet classification approach for multi-core systems. In our approach, novel data structures and four decomposition-based algorithms are designed to optimize the classification and updating of rules. For multi-field rules, a rule set is cut into several parts according to the number of fields. Each part works independently. In this way, the fields are searched in parallel and all the partial results are merged together at last. To demonstrate the feasibility of our approach, we implement a prototype and evaluate its throughput and latency. Experimental results show that our approach achieves a 40% higher throughput than that of other decomposed-based algorithms and a 43% lower latency of rule incremental update than that of the other algorithms on average. Furthermore, our approach saves 39% memory consumption on average and has a good scalability. 展开更多
关键词 multi-dimensional multi-core packet classification
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Modeling of Few-Mode Multi-Core Optical Fiber Channel Based on Non-Uniform Mode Field Distribution 认领 引用
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作者 Hang Zhou Bo Liu +6 位作者 Fu Wang Dandan Song Li Li Xiangjun Xin Qinghua Tian Qi Zhang Feng Tian 《China Communications》 SCIE CSCD 2016年第8期184-191,共8页
In this paper, the influencing factors that affect few-mode and multi core optical fiber channel are analyzed in a comprehensive way. The theoretical modeling and computer simulation of the information channel are car... In this paper, the influencing factors that affect few-mode and multi core optical fiber channel are analyzed in a comprehensive way. The theoretical modeling and computer simulation of the information channel are carried out and then the modeling scheme of few-mode multicore optical fiber channel based on non-uniform mode field distribution is put forward. The proposed modeling scheme can not only exponentially increases the system capacity through fewmode multi-core optical fiber channel, but has better transmission performance compared to the channel of the same type to the uniform channel revealing from the simulation results. 展开更多
关键词 few-mode multi-core optical fiber channel non-uniform channel channel modeling
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Variation-Aware Task Mapping on Homogeneous Fault-Tolerant Multi-Core Network-on-Chips 认领 引用
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作者 Chengbo Xue Yougen Xu +1 位作者 Yue Hao Wei Gao 《Journal of Beijing Institute of Technology》 EI CAS 2019年第3期497-509,共13页
A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time geneti... A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield. 展开更多
关键词 process variation task mapping fault-tolerant network-on-chips multi-core
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Theoretical Analysis on Inter-Core Crosstalk Suppression Model for Multi-Core Fiber 认领 引用
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作者 Jiajing Tu Xueqin Xie Keping Long 《China Communications》 SCIE CSCD 2016年第8期192-197,共6页
Decreasing mode coupling coefficient(κ) is an effective approach to suppress the inter-core crosstalk. Therefore, we deploy a low index rod and rectangle trench in the middle of two neighboring cores to reduce κ so ... Decreasing mode coupling coefficient(κ) is an effective approach to suppress the inter-core crosstalk. Therefore, we deploy a low index rod and rectangle trench in the middle of two neighboring cores to reduce κ so that the overlap of electric field distribution can be suppressed. We also propose approximate analytical solution(AAS) for κ of two crosstalk suppression models, which are two cores with one low index rod deployed in the middle and two cores with one low index rectangle trench deployed in the middle. We then do some modification for the results obtained by AAS and the modified results are proved to agree well with that obtained by finite element method(FEM). Therefore, we can use the modified AAS to get inter-core crosstalk for abovementioned two models quickly. 展开更多
关键词 multi-core fiber crosstalk mode coupling coefficient
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Cache performance optimization of irregular sparse matrix multiplication on modern multi-core CPU and GPU 认领 引用
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作者 刘力 LiuLi Yang Guang wen 《High Technology Letters》 EI CAS 2013年第4期339-345,共7页
This paper focuses on how to optimize the cache performance of sparse matrix-matrix multiplication(SpGEMM).It classifies the cache misses into two categories;one is caused by the irregular distribution pattern of the ... This paper focuses on how to optimize the cache performance of sparse matrix-matrix multiplication(SpGEMM).It classifies the cache misses into two categories;one is caused by the irregular distribution pattern of the multiplier-matrix,and the other is caused by the multiplicand.For each of them,the paper puts forward an optimization method respectively.The first hash based method removes cache misses of the 1 st category effectively,and improves the performance by a factor of 6 on an Intel 8-core CPU for the best cases.For cache misses of the 2nd category,it proposes a new cache replacement algorithm,which achieves a cache hit rate much higher than other historical knowledge based algorithms,and the algorithm is applicable on CELL and GPU.To further verify the effectiveness of our methods,we implement our algorithm on GPU,and the performance perfectly scales with the size of on-chip storage. 展开更多
关键词 sparse matrix multiplication cache miss scalability multi-core CPU GPU
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Shared Cache Based on Content Addressable Memory in a Multi-Core Architecture 认领 引用
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作者 Allam Abumwais Mahmoud Obaid 《Computers, Materials & Continua》 SCIE EI 2023年第3期4951-4963,共13页
Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to acc... Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to access the shared cache simultaneously.The main problem in improving memory performance is the shared cache architecture and cache replacement.This paper documents the implementation of a Dual-Port Content Addressable Memory(DPCAM)and a modified Near-Far Access Replacement Algorithm(NFRA),which was previously proposed as a shared L2 cache layer in a multi-core processor.Standard Performance Evaluation Corporation(SPEC)Central Processing Unit(CPU)2006 benchmark workloads are used to evaluate the benefit of the shared L2 cache layer.Results show improved performance of the multicore processor’s DPCAM and NFRA algorithms,corresponding to a higher number of concurrent accesses to shared memory.The new architecture significantly increases system throughput and records performance improvements of up to 8.7%on various types of SPEC 2006 benchmarks.The miss rate is also improved by about 13%,with some exceptions in the sphinx3 and bzip2 benchmarks.These results could open a new window for solving the long-standing problems with shared cache in multi-core processors. 展开更多
关键词 Multi-core processor shared cache content addressable memory dual port CAM replacement algorithm benchmark program
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Research on Multi-Core Processor Analysis for WCET Estimation 认领 引用
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作者 LUO Haoran HU Shuisong +2 位作者 WANG Wenyong TANG Yuke ZHOU Junwei 《ZTE Communications》 2024年第1期87-94,共8页
Real-time system timing analysis is crucial for estimating the worst-case execution time(WCET)of a program.To achieve this,static or dynamic analysis methods are used,along with targeted modeling of the actual hardwar... Real-time system timing analysis is crucial for estimating the worst-case execution time(WCET)of a program.To achieve this,static or dynamic analysis methods are used,along with targeted modeling of the actual hardware system.This literature review focuses on calculating WCET for multi-core processors,providing a survey of traditional methods used for static and dynamic analysis and highlighting the major challenges that arise from different program execution scenarios on multi-core platforms.This paper outlines the strengths and weaknesses of current methodologies and offers insights into prospective areas of research on multi-core analysis.By presenting a comprehensive analysis of the current state of research on multi-core processor analysis for WCET estimation,this review aims to serve as a valuable resource for researchers and practitioners in the field. 展开更多
关键词 real-time system worst-case execution time(WCET) multi-core analysis
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Asymmetry-aware load balancing for parallel applications in single-ISA multi-core systems 认领 引用
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作者 Eunsung KIM Hyeonsang EOM Heon Y. YEOM 《Journal of Zhejiang University-Science C(Computers and Electronics)》 2012年第6期413-427,共15页
Contemporary operating systems for single-ISA （instruction set architecture） multi-core systems attempt to distribute tasks equally among all the CPUs. This approach works relatively well when there is no difference... Contemporary operating systems for single-ISA （instruction set architecture） multi-core systems attempt to distribute tasks equally among all the CPUs. This approach works relatively well when there is no difference in CPU capability. However, there are cases in which CPU capability differs from one another. For instance, static capability asymmetry results from the advent of new asymmetric hardware, and dynamic capability asymmetry comes from the operating system （OS） outside noise caused from networking or I/O handling. These asymmetries can make it hard for the OS scheduler to evenly distribute the tasks, resulting in less efficient load balancing. In this paper, we propose a user-level load balaneer for parallel applications, called the ＇capability balancer＇, which recognizes the difference of CPU capability and makes subtasks share the entire CPU capability fairly. The balancer can coexist with the existing kemel-level load balancer without detrimenting the behavior of the kernel balancer. The capability balancer can fairly distribute CPU capability to tasks with very little overhead. For real workloads like the NAS Parallel Benchmark （NPB）, we have accomplished speedups of up to 9.8% and 8.5% in dynamic and static asymmetries, respectively. We have also experienced speedups of 13.3% for dynamic asymmetry and 24.1% for static asymmetry in a competitive environment. The impacts of our task selection policies, FIFO （first in, first out） and cache, were compared. The use of the cache policy led to a speedup of 5.3% in overall execution time and a decrease of 4.7% in the overall cache miss count, compared with the FIFO policy, which is used by default. 展开更多
关键词 Scheduler Load balancing Capability asymmetry OS noise Multi-core
Improved DES on Heterogeneous Multi-core Architecture 认领 引用
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作者 Zhenshan Bao Chong Chen Wenbo Zhang 《国际计算机前沿大会会议论文集》 EI 2018年第1期34-34,共1页
DES （Data Encryption Standard） is one of the most classical algo- rithms of cryptography and its higher security makes it hard to be broke for a very long time. However, along with the constant development of comput... DES （Data Encryption Standard） is one of the most classical algo- rithms of cryptography and its higher security makes it hard to be broke for a very long time. However, along with the constant development of computer technology, especially in the 21st century, DES cannot be applied widely because of its low efficiency. Recently, the novel heterogeneous multi-core architecture represented by APU （Accelerated Processing Unit）, provides a new solution for the above problems. APU integrates CPU and GPU in a ground- breaking manner and makes the algorithm to make full use of the performance advantage of heterogeneous multi-core system by realizing the HSA （Hetero- geneous System Architecture） standard. This paper realizes DES on the fresh APU processor. By analyzing the performance, two kinds of improved schemes are proposed. The experimental results show that the running efficiency of algorithm can be greatly improved by using APU with reasonable optimization. In the same way, the other DES-like algorithm would also be optimized on these heterogeneous multi-core architecture. 展开更多
关键词 Data Encryption Standard （DES） APUHeterogeneous multi-core architecture Heterogeneous computing
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Thread Private Variable Access Optimization Technique for Sunway High-Performance Multi-core Processors 认领 引用
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作者 Jinying Kong Kai Nie +2 位作者 Qinglei Zhou Jinlong Xu Lin Han 《国际计算机前沿大会会议论文集》 EI 2021年第1期180-189,共10页
The primary way to achieve thread-level parallelism on the Sunwayhigh-performance multicore processor is to use the OpenMP programming technique.To address the problem of low parallelism efficiency caused by slow acce... The primary way to achieve thread-level parallelism on the Sunwayhigh-performance multicore processor is to use the OpenMP programming technique.To address the problem of low parallelism efficiency caused by slow accessto thread private variables in the compilation of Sunway OpenMP programs, thispaper proposes a thread private variable access technique based on privilegedinstructions. The privileged instruction-based thread-private variable access techniquecentralizes the implementation of thread-private variables at the compilerlevel, eliminating the model switching overhead of invoking OS core processingand improving the speed of accessing thread-private variables. On the Sunway1621 server platform, NPB3.3-OMP and SPEC OMP2012 achieved 6.2% and6.8% running efficiency gains, respectively. The results show that the techniquesproposed in this paper can provide technical support for giving full play to theadvantages of Sunway’s high-performance multi-core processors. 展开更多
关键词 Sunway high-performance multi-core processors OpenMP programming technique Privileged instruction-based thread-private variable access technique Sunway 1621 processor
Parallel Region Reconstruction Technique for Sunway High-Performance Multi-core Processors 认领 引用
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作者 Kai Nie Qinglei Zhou +3 位作者 Hong Qian Jianmin Pang Jinlong Xu Yapeng Li 《国际计算机前沿大会会议论文集》 EI 2021年第1期163-179,共17页
The leading way to achieve thread-level parallelism on the Sunwayhigh-performance multicore processors is to use OpenMP programming techniques.In order to address the problem of low parallel efficiency caused by hight... The leading way to achieve thread-level parallelism on the Sunwayhigh-performance multicore processors is to use OpenMP programming techniques.In order to address the problem of low parallel efficiency caused by highthread group control overhead in the compilation of Sunway OpenMP programs,this paper proposes the parallel region reconstruction technique. The parallelregion reconstruction technique expands the parallel scope of parallel regionsin OpenMP programs by parallel region merging and parallel region extending.Moreover, it reduces the number of parallel regions in OpenMP programs,decreases the overhead of frequent creation and convergence of thread groups,and converts standard fork-join model OpenMP programs to higher performanceSPMD modelOpenMP programs. On the Sunway 1621 server computer, NPB3.3-OMP and SPEC OMP2012 achieved 8.9% and 7.9% running efficiency improvementrespectively through parallel region reconstruction technique. As a result,the parallel region reconstruction technique is feasible and effective. It providestechnical support to fully exploit the multi-core parallelism advantage of Sunway’shigh-performance processors. 展开更多
关键词 Sunway high-performance multi-core processors OpenMP programming technique Parallel domain reconstruction technique
Performance Behaviour Analysis of the Present 3-Level Cache System for Multi-Core Processors 认领 引用
20
作者 Muhammad Ali Ismail 《Computer Technology and Application》 2012年第11期729-733,共5页
In this paper, a study related to the expected performance behaviour of present 3-level cache system for multi-core systems is presented. For this a queuing model for present 3-level cache system for multi-core proces... In this paper, a study related to the expected performance behaviour of present 3-level cache system for multi-core systems is presented. For this a queuing model for present 3-level cache system for multi-core processors is developed and its possible performance has been analyzed with the increase in number of cores. Various important performance parameters like access time and utilization of individual cache at different level and overall average access time of the cache system is determined. Results for up to 1024 cores have been reported in this paper. 展开更多
关键词 Multi-core memory hierarchy cache access time queuing analysis.
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