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Multi-core optimization for conjugate gradient benchmark on heterogeneous processors 认领 引用
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作者 邓林 窦勇 《Journal of Central South University》 SCIE EI CAS 2011年第2期490-498,共9页
Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at t... Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at this problem,a parallelization approach was proposed with six memory optimization schemes for CG,four schemes of them aiming at all kinds of sparse matrix-vector multiplication (SPMV) operation. Conducted on IBM QS20,the parallelization approach can reach up to 21 and 133 times speedups with size A and B,respectively,compared with single power processor element. Finally,the conclusion is drawn that the peak bandwidth of memory access on Cell BE can be obtained in SPMV,simple computation is more efficient on heterogeneous processors and loop-unrolling can hide local storage access latency while executing scalar operation on SIMD cores. 展开更多
关键词 multi-core processor NAS parallelization CG memory optimization
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Thread Private Variable Access Optimization Technique for Sunway High-Performance Multi-core Processors 认领 引用
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作者 Jinying Kong Kai Nie +2 位作者 Qinglei Zhou Jinlong Xu Lin Han 《国际计算机前沿大会会议论文集》 EI 2021年第1期180-189,共10页
The primary way to achieve thread-level parallelism on the Sunwayhigh-performance multicore processor is to use the OpenMP programming technique.To address the problem of low parallelism efficiency caused by slow acce... The primary way to achieve thread-level parallelism on the Sunwayhigh-performance multicore processor is to use the OpenMP programming technique.To address the problem of low parallelism efficiency caused by slow accessto thread private variables in the compilation of Sunway OpenMP programs, thispaper proposes a thread private variable access technique based on privilegedinstructions. The privileged instruction-based thread-private variable access techniquecentralizes the implementation of thread-private variables at the compilerlevel, eliminating the model switching overhead of invoking OS core processingand improving the speed of accessing thread-private variables. On the Sunway1621 server platform, NPB3.3-OMP and SPEC OMP2012 achieved 6.2% and6.8% running efficiency gains, respectively. The results show that the techniquesproposed in this paper can provide technical support for giving full play to theadvantages of Sunway’s high-performance multi-core processors. 展开更多
关键词 Sunway high-performance multi-core processors OpenMP programming technique Privileged instruction-based thread-private variable access technique Sunway 1621 processor
Parallel Region Reconstruction Technique for Sunway High-Performance Multi-core Processors 认领 引用
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作者 Kai Nie Qinglei Zhou +3 位作者 Hong Qian Jianmin Pang Jinlong Xu Yapeng Li 《国际计算机前沿大会会议论文集》 EI 2021年第1期163-179,共17页
The leading way to achieve thread-level parallelism on the Sunwayhigh-performance multicore processors is to use OpenMP programming techniques.In order to address the problem of low parallel efficiency caused by hight... The leading way to achieve thread-level parallelism on the Sunwayhigh-performance multicore processors is to use OpenMP programming techniques.In order to address the problem of low parallel efficiency caused by highthread group control overhead in the compilation of Sunway OpenMP programs,this paper proposes the parallel region reconstruction technique. The parallelregion reconstruction technique expands the parallel scope of parallel regionsin OpenMP programs by parallel region merging and parallel region extending.Moreover, it reduces the number of parallel regions in OpenMP programs,decreases the overhead of frequent creation and convergence of thread groups,and converts standard fork-join model OpenMP programs to higher performanceSPMD modelOpenMP programs. On the Sunway 1621 server computer, NPB3.3-OMP and SPEC OMP2012 achieved 8.9% and 7.9% running efficiency improvementrespectively through parallel region reconstruction technique. As a result,the parallel region reconstruction technique is feasible and effective. It providestechnical support to fully exploit the multi-core parallelism advantage of Sunway’shigh-performance processors. 展开更多
关键词 Sunway high-performance multi-core processors OpenMP programming technique Parallel domain reconstruction technique
Shared Cache Based on Content Addressable Memory in a Multi-Core Architecture 认领 引用
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作者 Allam Abumwais Mahmoud Obaid 《Computers, Materials & Continua》 SCIE EI 2023年第3期4951-4963,共13页
Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to acc... Modern shared-memory multi-core processors typically have shared Level 2(L2)or Level 3(L3)caches.Cache bottlenecks and replacement strategies are the main problems of such architectures,where multiple cores try to access the shared cache simultaneously.The main problem in improving memory performance is the shared cache architecture and cache replacement.This paper documents the implementation of a Dual-Port Content Addressable Memory(DPCAM)and a modified Near-Far Access Replacement Algorithm(NFRA),which was previously proposed as a shared L2 cache layer in a multi-core processor.Standard Performance Evaluation Corporation(SPEC)Central Processing Unit(CPU)2006 benchmark workloads are used to evaluate the benefit of the shared L2 cache layer.Results show improved performance of the multicore processor’s DPCAM and NFRA algorithms,corresponding to a higher number of concurrent accesses to shared memory.The new architecture significantly increases system throughput and records performance improvements of up to 8.7%on various types of SPEC 2006 benchmarks.The miss rate is also improved by about 13%,with some exceptions in the sphinx3 and bzip2 benchmarks.These results could open a new window for solving the long-standing problems with shared cache in multi-core processors. 展开更多
关键词 Multi-core processor shared cache content addressable memory dual port CAM replacement algorithm benchmark program
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swDaCe:一种申威众核处理器上以数据为中心的并行编程模型设计与实现 认领 引用
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作者 沈沛祺 陈俊仕 安虹 《小型微型计算机系统》 CSCD 北大核心 2026年第3期751-759,共9页
高性能科学计算是超级计算机的核心应用领域,包括粒子模拟、气候分析等关键任务.然而,随着摩尔定律逐渐失效,超级计算机体系结构日益趋向异构和复杂,导致科学计算应用的开发和优化变得更加困难.为解决这一问题,本文基于新一代申威超级... 高性能科学计算是超级计算机的核心应用领域,包括粒子模拟、气候分析等关键任务.然而,随着摩尔定律逐渐失效,超级计算机体系结构日益趋向异构和复杂,导致科学计算应用的开发和优化变得更加困难.为解决这一问题,本文基于新一代申威超级计算平台,提出并实现了一种以数据为中心的并行编程模型——swDaCe.该模型通过解耦数据流图优化与原始程序,使得编程人员可以使用Python描述计算逻辑,并最终生成适配申威众核架构的高性能C++代码.此外,本文提出了一系列针对申威架构的数据流优化方法,包括从核任务映射、向量化并行以及DMA访存优化,以充分利用申威众核处理器的计算能力.实验结果表明,swDaCe生成的代码在稀疏矩阵计算等典型应用中实现了显著的性能提升,单核组加速比达到25倍以上,验证了该框架在申威架构上的有效性. 展开更多
关键词 新一代神威平台 异构众核处理器 数据流编程 并行计算 稀疏矩阵乘
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基于指令串行融合的RISC-V向量处理器计算方法 认领 引用
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作者 李凯歌 高鑫 杨孟飞 《微电子学与计算机》 2026年第3期155-163,共9页
在传统冯诺依曼计算机架构中,卷积神经网络、矩阵计算与快速傅里叶变换等算法存在频繁的数据重用,导致向量处理器流水线中产生大量写后读指令,易引发数据冲突。同时,数据在向量寄存器和计算单元之间的反复传输带来了显著的功耗开销。针... 在传统冯诺依曼计算机架构中,卷积神经网络、矩阵计算与快速傅里叶变换等算法存在频繁的数据重用,导致向量处理器流水线中产生大量写后读指令,易引发数据冲突。同时,数据在向量寄存器和计算单元之间的反复传输带来了显著的功耗开销。针对上述问题,提出了一种面向向量计算的数据冲突解决机制。通过利用数据重用减少数据流动,从而降低计算芯片功耗。将该方法应用于RISC-V向量处理器的仿真实验表明:在128×128矩阵乘法计算时,整体芯片功耗降低约5.8%;在计算神经卷积网络算法时,功耗降低约6.2%。该方法具有轻量化的特点,所引入的面积开销可忽略不计。 展开更多
关键词 RISC-V 向量处理器 矩阵计算 能效
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System Architecture of Godson-3 Multi-Core Processors 认领 引用 被引量：19
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作者 高翔 陈云霁 +2 位作者 王焕东 唐丹 胡伟武 《Journal of Computer Science & Technology》 SCIE EI 2010年第2期181-191,共11页
Godson-3 is the latest generation of Godson microprocessor family. It takes a scalable multi-core architecture with hardware support for accelerating applications including X86 emulation and signal processing. This pa... Godson-3 is the latest generation of Godson microprocessor family. It takes a scalable multi-core architecture with hardware support for accelerating applications including X86 emulation and signal processing. This paper introduces the system architecture of Godson-3 from various aspects including system scalability, organization of memory hierarchy, network-on-chip, inter-chip connection and I/O subsystem. 展开更多
关键词 multi-core processor scalable interconnection cache coherent non-uniform memory accesson-uniform cache access （CC-NUMA/NUCA） MESH crossbar cache coherence reliability availability and serviceability （RAS）
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Compressing and expanding optical matrix-vector multipliers for enabling optical image encoder-decoders and generators 认领 引用
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作者 Adrian Stern 《Light: Science & Applications》 SCIE EI CAS CSCD 2026年第2期363-365,共3页
Both compressing and expanding optical matrix-vector multipliers are necessary for the full optical realization of neural networks.An expanding multiplier scheme is proposed,which,together with common compressing mult... Both compressing and expanding optical matrix-vector multipliers are necessary for the full optical realization of neural networks.An expanding multiplier scheme is proposed,which,together with common compressing multipliers,is employed to demonstrate image processor networks such as autoencoders and image generators. 展开更多
关键词 neural networksan common compressing multipliersis image generators full optical realization optical matrix vector multipliers image processor networks compressing multipliers expanding multiplier
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面向SW26010-Pro众核处理器的新型矩阵存储格式及稀疏矩阵向量乘(SpMV)算法研究 认领 引用 被引量：1
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作者 王萃 刘芳芳 +2 位作者 马文静 赵玉文 胡力娟 《计算机学报》 EI CAS CSCD 北大核心 2025年第6期1290-1304,共15页
稀疏矩阵向量乘(Sparse Matrix-Vector Multiplication,SpMV)是高性能计算、人工智能大模型领域中的关键操作,其性能通常对应用程序整体性能的提升具有重要影响。高效的稀疏矩阵存储格式是影响SpMV性能的重要因素,然而,现有的稀疏矩阵... 稀疏矩阵向量乘(Sparse Matrix-Vector Multiplication,SpMV)是高性能计算、人工智能大模型领域中的关键操作,其性能通常对应用程序整体性能的提升具有重要影响。高效的稀疏矩阵存储格式是影响SpMV性能的重要因素,然而,现有的稀疏矩阵存储格式主要通过压缩零元素以减少访存,未充分利用非零元素的数值规律,因此仍有进一步压缩和优化的空间。本文通过对压缩稀疏行(Compressed Sparse Row,CSR)存储格式中非零元数组内的重复元素进行进一步的压缩,提出了一种新型的稀疏矩阵存储格式(Further Compressed Sparse Row,FCSR),并设计了从CSR到FCSR格式转换的异构并行算法,以尽量减少格式转换带来的开销。同时,本文面向SW26010-Pro众核处理器,设计了基于FCSR存储格式的SpMV异构并行算法,对SpMV进行了细粒度的任务划分和并行优化设计,探究了五种向量x的间接访存方式,并通过双缓冲技术对算法进行了优化。最后,本文选用SuiteSparse矩阵集中的稀疏矩阵进行了测试,实验结果表明,本文提出的基于FCSR存储格式的异构众核SpMV算法相较于主核版SpMV算法具有明显的性能提升,最高加速比达到43.11,平均加速比为7.56,测试矩阵最高带宽利用率达到了91.13%,平均带宽利用率为26.27%。另外,本文对基于FCSR存储格式和CSR存储格式的SpMV算法性能进行了比较,在两者均得到充分优化的前提下,基于FCSR存储格式的SpMV算法相较于基于CSR存储格式的SpMV算法性能的平均加速比达到1.19。 展开更多
关键词 稀疏矩阵向量乘 SW26010-Pro众核处理器 新型矩阵存储格式 并行优化 双缓冲技术
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MT-office:parallel password recovery program for office on domestic heterogeneous multi-core processor 认领 引用 被引量：2
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作者 Yongtao Luo Bo Yang +5 位作者 Jie Liu Ruibo Wang Jinmin Wen Tiaojie Xiao Xuguang Chen Chunye Gong 《CCF Transactions on High Performance Computing》 EI 2023年第3期231-244,共14页
With the improvement of security awareness,in order to guarantee information security,more advanced and secure encryption algorithms are applied to Microsoft Office.People also set more complex encryption passwords.Ho... With the improvement of security awareness,in order to guarantee information security,more advanced and secure encryption algorithms are applied to Microsoft Office.People also set more complex encryption passwords.However,once the initial password is forgotten,the encrypted information needs to be retrieved.The conventional brute force cracking methods and password recovery programs can hardly meet the actual deciphering needs.To this end,we develop a distributed parallel password recovery program(MT-Office)for Microsoft Office on the domestic heterogeneous multi-core processor(MT-3000).MT-Office takes full advantage of the multi-core and heterogeneous features of MT-3000,and is optimized and improved in both vectorization and global computing.At the same time,MT-Office provides multiple recovery strategies in password generation to improve the recovery efficiency.Compared with other platforms(e.g.,Intel platforms and FT platforms),MT-3000 heterogeneous platform can achieve 60×–218×speedup ratio.For Office2010,we perform a strong scalability test on the new-generation supercomputer in National Supercomputer Center in Tianjin.MT-Office not only extends to 65,536 acceleration clusters on this system,shows good scalability,but also achieves almost linear speedup ratio.For Office2007,compared with other password recovery programs,MT-Office can achieve 2.5×–131.1×speedup ratio.It can be seen that MT-Office can better exploit the advantages of MT-3000,which not only has good scalability and parallelism,but also has faster deciphering speed and can be applied to practical engineering application. 展开更多
关键词 Office password recovery Heterogeneous multi-core processor SIMD Heterogeneous computing
Schedule refinement for homogeneous multi-core processors in the presence of manufacturing-caused heterogeneity 认领 引用 被引量：1
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作者 Zhi-xiang CHEN Zhao-lin LI +2 位作者 Shan CAO Fang WANG Jie ZHOU 《Frontiers of Information Technology & Electronic Engineering》 SCIE EI CSCD 2015年第12期1018-1033,共16页
Multi-core homogeneous processors have been widely used to deal with computation-intensive embedded applications. However, with the continuous down scaling of CMOS technology, within-die variations in the manufacturin... Multi-core homogeneous processors have been widely used to deal with computation-intensive embedded applications. However, with the continuous down scaling of CMOS technology, within-die variations in the manufacturing process lead to a significant spread in the operating speeds of cores within homogeneous multi-core processors. Task scheduling approaches, which do not consider such heterogeneity caused by within-die variations,can lead to an overly pessimistic result in terms of performance. To realize an optimal performance according to the actual maximum clock frequencies at which cores can run, we present a heterogeneity-aware schedule refining(HASR) scheme by fully exploiting the heterogeneities of homogeneous multi-core processors in embedded domains.We analyze and show how the actual maximum frequencies of cores are used to guide the scheduling. In the scheme,representative chip operating points are selected and the corresponding optimal schedules are generated as candidate schedules. During the booting of each chip, according to the actual maximum clock frequencies of cores, one of the candidate schedules is bound to the chip to maximize the performance. A set of applications are designed to evaluate the proposed scheme. Experimental results show that the proposed scheme can improve the performance by an average value of 22.2%, compared with the baseline schedule based on the worst case timing analysis. Compared with the conventional task scheduling approach based on the actual maximum clock frequencies, the proposed scheme also improves the performance by up to 12%. 展开更多
关键词 Schedule refining Multi-core processor Heterogeneity Representative chip operating point
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Parallel computing of discrete element method on multi-core processors 认领 引用 被引量：7
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作者 Yusuke Shigeto Mikio Sakai 《Particuology》 SCIE EI CAS CSCD 2011年第4期398-405,共8页
This paper describes parallel simulation techniques for the discrete element method （DEM） on multi-core processors. Recently, multi-core CPU and GPU processors have attracted much attention in accelerating computer ... This paper describes parallel simulation techniques for the discrete element method （DEM） on multi-core processors. Recently, multi-core CPU and GPU processors have attracted much attention in accelerating computer simulations in various fields. We propose a new algorithm for multi-thread parallel computation of DEM, which makes effective use of the available memory and accelerates the computation. This study shows that memory usage is drastically reduced by using this algorithm. To show the practical use of DEM in industry, a large-scale powder system is simulated with a complicated drive unit. We compared the performance of the simulation between the latest GPU and CPU processors with optimized programs for each processor. The results show that the difference in performance is not substantial when using either GPUs or CPUs with a multi-thread parallel algorithm. In addition, DEM algorithm is shown to have high scalabilitv in a multi-thread parallel computation on a CPU. 展开更多
关键词 Discrete element method Parallel computing Multi-core processor GPGPU
海光处理器上后量子签名算法的AVX2优化实现 认领 引用
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作者 王悦彤 周璐 +1 位作者 杨昊 刘哲 《计算机学报》 EI CAS CSCD 北大核心 2025年第7期1714-1732,共19页
随着量子计算技术的快速发展,传统密码体系面临着巨大的安全威胁,后量子密码学(PQC)的研究迫在眉睫。在此背景下,格密码凭借其出色的抗量子攻击能力,成为后量子数字签名算法的重要基础。HuFu算法是我国自主研发的后量子数字签名算法,基... 随着量子计算技术的快速发展,传统密码体系面临着巨大的安全威胁,后量子密码学(PQC)的研究迫在眉睫。在此背景下,格密码凭借其出色的抗量子攻击能力,成为后量子数字签名算法的重要基础。HuFu算法是我国自主研发的后量子数字签名算法,基于格密码学中的通用格问题,具有良好的安全性和应用前景,目前已提交至美国国家标准技术研究院(NIST)进行标准化评估。但HuFu算法在性能上仍有提升空间,特别是在算法复杂度、内存效率和并行计算能力方面,同时还需增强对不同硬件和指令集的兼容性。为此,本文基于国产的海光处理器,充分发挥其高并行性、低能耗和高吞吐量的优势,为HuFu算法的高效实现提供了强有力的硬件支持。同时,结合256位高级向量扩展(AVX2)指令集,这一广泛应用的单指令多数据(SIMD)技术,进一步增强了算法的并行计算能力,从而有效提升了整体性能。本文综合考虑矩阵乘法优化、指令集加速、编码处理简化和内存访问效率等多个方面,采用一系列算法和技术优化,旨在显著提升计算速度、减少资源消耗,并提高签名生成与验证的整体性能。具体而言,本文的优化方案包括多个关键技术点:首先,结合Strassen算法优化矩阵乘法,显著提升了计算速度并减少了资源消耗;其次,采用AVX2指令集对非对称数字的范围变体编码(rANS)进行了优化,加快了签名生成与验证的速度;此外,针对rANS编码中符号位处理复杂且耗时的问题,采用无符号参数来实现高效的签名和验证处理,简化了计算流程并减少了运算开销;最后,通过设计合理的函数接口和内存访问优化技术,提高了签名和验证阶段的内存使用效率,减少了寄存器的频繁写入。与原有的HuFu算法AVX2实现方案相比,本文提出的优化方案在密钥生成、签名在线阶段、签名离线阶段以及总的签名和验证阶段的时钟周期消耗分别减少了约46%、54%、45%、30%和46%。高效的签名算法能够在高并发环境中提升处理能力,增强系统的稳定性和安全性,更好地保护后量子密码数据免受量子计算威胁,同时推动国产后量子密码技术的发展。 展开更多
关键词 后量子密码 格密码 高级向量拓展 矩阵乘法 内存访问优化 海光处理器
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基于FT-MT的RDSAR算法优化实现 认领 引用
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作者 郑利华 杨辉 +2 位作者 文楚 王耀华 时洋 《计算机应用文摘》 2025年第9期88-93,96,共6页
合成雷达孔径(Synthetic Aperture Radar,SAR)成像回波数据量大且算法复杂,这使得其在实时应用中的实现面临挑战。针对国防科技大学自主研制的高性能异构多核数字信号处理器(Digital Signal Processor,DSP)FT-MT的体系结构特征及距离-... 合成雷达孔径(Synthetic Aperture Radar,SAR)成像回波数据量大且算法复杂,这使得其在实时应用中的实现面临挑战。针对国防科技大学自主研制的高性能异构多核数字信号处理器(Digital Signal Processor,DSP)FT-MT的体系结构特征及距离-多普勒(Range-Doppler,RD)SAR成像算法的特点,设计了一种面向多核DSP架构的高性能并行RD SAR算法。该算法基于DSP的向量部件,实现了有限脉冲响应滤波(Finite Impulse Response,FIR)、行向和列向快速傅里叶变换(Fast Fourier Transform,FFT)以及快速傅里叶逆变换(Inverse Fast Fourier Transform,IFFT)的向量化计算。同时,结合算子融合、双缓冲和多核并行的优化策略,充分发挥FT-MT架构的优势,显著提升了计算密集型算法的运行效率。实验结果表明,采用并行RD SAR算法相比传统的串行算法具有明显的性能优势;在1.0 GHz频率下,FT-MT单个DSP核处理512 kB(1024×512)图像的时间为23.23 ms,而与德州仪器(Texas Instruments,TI)TMS320C6678在1.2 GHz频率下的单核运行相比,性能加速比可高达20.536;FT-MT四核并行处理512 kB图像的时间为6.089 ms,成功实现了实时性。 展开更多
关键词 合成孔径雷达 多核数字信号处理器 距离-多普勒 向量化
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Energy Efficiency of a Multi-Core Processor by Tag Reduction 认领 引用
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作者 郑龙 董冕雄 +3 位作者 Kaoru Ota 金海 Song Guo 马俊 《Journal of Computer Science & Technology》 SCIE EI CSCD 2011年第3期491-503,共13页
We consider the energy saving problem for caches on a multi-core processor. In the previous research on low power processors, there are various methods to reduce power dissipation. Tag reduction is one of them. This p... We consider the energy saving problem for caches on a multi-core processor. In the previous research on low power processors, there are various methods to reduce power dissipation. Tag reduction is one of them. This paper extends the tag reduction technique on a single-core processor to a multi-core processor and investigates the potential of energy saving for multi-core processors. We formulate our approach as an equivalent problem which is to find an assignment of the whole instruction pages in the physical memory to a set of cores such that the tag-reduction conflicts for each core can be mostly avoided or reduced. We then propose three algorithms using different heuristics for this assignment problem. We provide convincing experimental results by collecting experimental data from a real operating system instead of the traditional way using a processor simulator that cannot simulate operating system functions and the full memory hierarchy. Experimental results show that our proposed algorithms can save total energy up to 83.93% on an 8-core processor and 76.16% on a 4-core processor in average compared to the one that the tag-reduction is not used for. They also significantly outperform the tag reduction based algorithm on a single-core processor. 展开更多
关键词 tag reduction multi-core processor energy efficiency
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便携式矢量信号源的设计 认领 引用
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作者 李敬军 王博 李力 《今日自动化》 2025年第3期67-70,共4页
在雷达和通信测试中,常需要信号源模拟一些特殊多变的信号,如无线信道模拟、复杂电磁环境模拟等。针对这一需求,文章设计了一款灵活性高、适应性强的多通道便携式矢量信号源,介绍了该信号源的硬件电路及控制逻辑设计,并通过系统测试验... 在雷达和通信测试中,常需要信号源模拟一些特殊多变的信号,如无线信道模拟、复杂电磁环境模拟等。针对这一需求,文章设计了一款灵活性高、适应性强的多通道便携式矢量信号源,介绍了该信号源的硬件电路及控制逻辑设计,并通过系统测试验证了该信号源的可行性。 展开更多
关键词 矢量信号源 AD9361 零中频架构 基带处理器
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MVSim:面向VLIW多核向量处理器的快速、可扩展和精确的体系结构模拟器 认领 引用 被引量：4
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作者 刘仲 李程 +3 位作者 田希 刘胜 邓让钰 钱程东 《计算机工程与科学》 CSCD 北大核心 2024年第2期191-199,共9页
设计了一个面向VLIW多核向量处理器的快速、可扩展、精确的体系结构模拟器MVSim。设计了可扩展的VLIW多核向量处理器模型、多级存储体系结构模型和多核性能模型;实现了指令集架构的节拍精准模拟,Cache、DMA和多核同步部件的高效功能模拟... 设计了一个面向VLIW多核向量处理器的快速、可扩展、精确的体系结构模拟器MVSim。设计了可扩展的VLIW多核向量处理器模型、多级存储体系结构模型和多核性能模型;实现了指令集架构的节拍精准模拟,Cache、DMA和多核同步部件的高效功能模拟,采用多线程技术实现了多核处理器的高效和可扩展模拟。实验结果表明,MVSim能够准确模拟多核处理器的目标程序执行,模拟结果完全正确,具有良好的可扩展性。MVSim的平均模拟速度分别是RTL模拟和CCS的227倍和5倍,平均性能误差约为2.9%。 展开更多
关键词 体系结构模拟器 VLIW 多核向量处理器模型 性能模型 节拍精准模拟器
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面向多核向量处理器的矩阵乘法向量化方法 认领 引用 被引量：9
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作者 刘仲 田希 《计算机学报》 EI CAS CSCD 北大核心 2018年第10期2251-2264,共14页
稠密矩阵乘法是大规模科学计算中许多算法的核心计算之一,文中提出一种高效的面向多核向量处理器的矩阵乘法向量化方法.提出一种按行计算的矩阵乘法向量化方法,该向量化方法的基本思想是每次同时计算C矩阵的一行元素,C矩阵第i行元素的值... 稠密矩阵乘法是大规模科学计算中许多算法的核心计算之一,文中提出一种高效的面向多核向量处理器的矩阵乘法向量化方法.提出一种按行计算的矩阵乘法向量化方法,该向量化方法的基本思想是每次同时计算C矩阵的一行元素,C矩阵第i行元素的值由k次向量乘累加完成,每次计算都是先将A矩阵第i行的第j个元素扩展为值相同的向量,再与B矩阵的第j行向量进行乘累加计算,每一次的向量乘累加计算是在各个VPE上并行进行,计算的源数据和结果数据均保存在VPE的本地寄存器上,每个计算结果涉及的乘累加计算均在同一个VPE上完成,并且A、B、C三个矩阵的数据均是按行顺序读取,访存效率高,在k循环结束时,同时完成C矩阵第i行元素值的计算.该方法能充分开发向量处理器的标量、向量协同数据加载能力,有效减少对DDR的存储带宽需求,能够避免低效的对乘数矩阵列向量数据的访问和各个VPE间的浮点归约求和计算,取得最优的内核计算性能;将处理器的一级数据缓存和阵列存储配置为SRAM访问模式,能够避免由于Cache数据不命中而导致的存储访问延迟,提高核心计算访问一级数据缓存和阵列存储的效率,采用组播DMA传输矩阵数据,能够显著提高从DDR读取矩阵数据的效率;提出依据向量处理单元VPE数量、VPE的FMAC运算单元数量、向量存储器的容量和矩阵元素的数据类型等向量处理器体系结构特点设计最优的核心子块矩阵分块参数设计方法,能够充分开发向量处理器的多核间数据并行、核内的多VPE间的向量SIMD并行、VPE内的多个FMAC单元并行、VPE内的标、向量指令级并行等多级并行性,并根据FMAC指令延迟槽进行完全循环展开,让内核始终以峰值速度运行;提出基于两级DMA双缓冲数据搬移策略,优化和平滑多级存储结构间的数据传输,使得DMA的数据搬移时间完全重叠于内核的计算时间中,让整个矩阵计算以接近内核计算的速度运行,实现最优的计算性能和效率.在MATRIX2上的实验结果表明,提出的双精度矩阵乘法的性能达到1106.88GFLOPS,效率为96.08%,核心计算的效率达到99.39%. 展开更多
关键词 多核向量处理器 高性能计算 矩阵乘法 分块矩阵 向量化
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YHFT-QDSP:High-Performance Heterogeneous Multi-Core DSP 认领 引用 被引量：7
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作者 陈书明 万江华 +8 位作者 鲁建壮 刘仲 孙海燕 孙永节 刘衡竹 刘祥远 李振涛 徐毅 陈小文 《Journal of Computer Science & Technology》 SCIE EI 2010年第2期214-224,共11页
Multi-core architectures are widely used to in time-to-market and power consumption of the chips enhance the microprocessor performance within a limited increase Toward the application of high-density data signal proc... Multi-core architectures are widely used to in time-to-market and power consumption of the chips enhance the microprocessor performance within a limited increase Toward the application of high-density data signal processing, this paper presents a novel heterogeneous multi-core architecture digital signal processor （DSP）, YHFT-QDSP, with one RISC CPU core and 4 VLIW DSP cores. By three kinds of interconnection, YHFT-QDSP provides high efficiency message communication for inner-chip RISC core and DSP cores, inner-chip and inter-chip DSP cores. A parallel programming platform is specifically developed for the heterogeneous nmlti-core architecture of YHFT-QDSP. This parallel programming environment provides a parallel support library and a friendly interface between high level application softwares and multi- core DSP. The 130 nm CMOS custom chip design results benchmarks show that the interconnection structure of in a high speed and moderate power design. The results of typical YHFT-QDSP is much better than other related structures and achieves better speedup when using the interconnection facilities in combing methods. YHFT-QDSP has been signed off and manufactured presently. The future applications of the multi-core chip could be found in 3G wireless base station, high performance radar, industrial applications, and so on. 展开更多
关键词 digital signal processor （DSP） multi-core architecture parallel programming custom design
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基于并行技术的大规模矢量地图可视化方法 认领 引用 被引量：6
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作者 张立强 徐翔 谭继强 《地理与地理信息科学》 CSCD 北大核心 2013年第4期9-12,共4页
随着测绘、遥感及相关技术的发展,矢量地图的数据规模和细节层次迅速增加,它们含有大量复杂地理空间要素,且要素间存在复杂的拓扑几何关系,使得大规模矢量地图的快速可视化对于高性能并行计算的需求十分迫切。为了实现大数据量矢量地图... 随着测绘、遥感及相关技术的发展,矢量地图的数据规模和细节层次迅速增加,它们含有大量复杂地理空间要素,且要素间存在复杂的拓扑几何关系,使得大规模矢量地图的快速可视化对于高性能并行计算的需求十分迫切。为了实现大数据量矢量地图实时可视化,提出了基于多核CPU和GPU的矢量地图快速可视化的方法。在GPU进行并行计算的同时,利用多核CPU创建多线程进行数据读写,隐藏数据I/O时间,提高显示的实时性。实验表明,与串行方法相比,该文的并行方法在大数据量矢量地图简化和可视化效率上有了极大提高。 展开更多
关键词 矢量地图 并行算法 多核处理器 GPU
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