An object-oriented C++ parallel compiler System, called OOCPCS, is developed to facilitate programmers to write sequential programs using C++ or Annotated C++ language for parallel computahon. OOCPCS bases on an integ...An object-oriented C++ parallel compiler System, called OOCPCS, is developed to facilitate programmers to write sequential programs using C++ or Annotated C++ language for parallel computahon. OOCPCS bases on an integrated object-oriented paradigm and large-grain data flow model, called OOLGDFM, and recognizes automatically parallel objects using parallel compiling techniques. The paper describes the object-oriented parallel model and realization of the System on networks.展开更多
A systolic array architecture computer (FXCQ) has been designed for signal processing. R can handle floating point data at very high speed. It is composed of 16 processing cells and a cache that are connected linearly...A systolic array architecture computer (FXCQ) has been designed for signal processing. R can handle floating point data at very high speed. It is composed of 16 processing cells and a cache that are connected linearly and form a ring structure. All processing cells are identical and programmable. Each processing cell has the peak performance of 20 million floating-point operations per second (20MFLOPS). The machine therefore has a peak performance of 320 M FLOPS. It is integrated as an attached processor into a host system through VME bus interface. Programs for FXCQ are written in a high-level language -B language, which is supported by a parallel optimizing compiler. This paper describes the architecture of FXCQ, B language and its compiler.展开更多
An object-oriented approach is taken to the problem of formulating portable, easy-to-modify PDE solvers for realistic problems in three space dimensions. The resulting software library, Cogito, contains tools for writ...An object-oriented approach is taken to the problem of formulating portable, easy-to-modify PDE solvers for realistic problems in three space dimensions. The resulting software library, Cogito, contains tools for writing programs to be executed on MIMD computers with distributed memory. Difference methods on composite, structured grids are supported. Most of the Cogito classes have been implemented in Fortran 77, in such a way that the object-oriented design is visible. With respect to parallel performance, these tools yield code that is comparable to parallel solvers written in plain Fortran 77. The resulting programs are can be executed without modification on a large number of multicomputer platforms, and also on serial computers. The uppermost level of abstraction in Cogito concerns the problem of decoupling the numerical method from the PDE problem. The validity of these tools has been preliminarily demonstrated with a C++ implementation for one-dimensional problems.展开更多
To improve the inference efficiency of convolutional neural networks(CNN),the existing neural networks mainly adopt heuristic and dynamic programming algorithms to realize parallel scheduling among operators.Heuristic...To improve the inference efficiency of convolutional neural networks(CNN),the existing neural networks mainly adopt heuristic and dynamic programming algorithms to realize parallel scheduling among operators.Heuristic scheduling algorithms can generate local optima easily,while the dynamic programming algorithm has a long convergence time for complex structural models.This paper mainly studies the parallel scheduling between operators and proposes an inter-operator parallelism schedule(IOPS)scheduling algorithm that guarantees the minimum similar execution delay.Firstly,a graph partitioning algorithm based on the largest block is designed to split the neural network model into multiple subgraphs.Then,the operators that meet the conditions is replaced according to the defined operator replacement rules.Finally,the optimal scheduling method based on backtracking is used to schedule the computational graph.Network models such as Inception-v3,ResNet-50,and RandWire are selected for testing.The experimental results show that the algorithm designed in this paper can achieve a 1.6×speedup compared with the existing sequential execution methods.展开更多
The currently available compilation techniques are for general computing and are not optimized for physical layer computing in 5G micro base stations.In such cases,the foreseeable data sizes and small code size are ap...The currently available compilation techniques are for general computing and are not optimized for physical layer computing in 5G micro base stations.In such cases,the foreseeable data sizes and small code size are application specific opportunities for baseband algorithm optimizations.Therefore,the special attention can be paid,for example,the specific register allocation algorithm has not been studied so far.The compilation for kernel sub-routines of baseband in 5G micro base stations is our focusing point.For applications of known and fixed data size,we proposed a compilation scheme of parallel data accessing,while operands can be mainly allocated and stored in registers.Based on a small register group(48×32b),the target of our compilation scheme is the optimization of baseband algorithms based on 4×4 or smaller matrices,maximizing the utilization of register files,and eliminating the extra register data exchanging.Meanwhile,when data is allocated into register files,we used VLIW(Very Long Instruction Word)machine to hide the time of data accessing and minimize the cost of data accessing,thus the total execution time is minimum.Experiments indicate that for algorithms with small data size,the cost of data accessing and extra addressing can be minimized.展开更多
At present, there are some static code analyses and optimizations that can be applied to Concurrent C programs to improve their performance or verify their logical correctness. These analyses and optimizations are int...At present, there are some static code analyses and optimizations that can be applied to Concurrent C programs to improve their performance or verify their logical correctness. These analyses and optimizations are inter-process. In order to make their implementation easy, we propose a new method to construct an optimizing compiling system CCOC for Concurrent C. CCOC supports inter-process code analysis and optimization to Concurrent C programs and does not affect the system's portability and separate compilation of source programs. We also discuss some implementation details of CCOC briefly.展开更多
For the moment, commercial parallel computer systems with distributed memory architecture are usually provided with parallel FORTRAN or parallel C compliers, which are just traditional sequential FORTRAN or C compiler...For the moment, commercial parallel computer systems with distributed memory architecture are usually provided with parallel FORTRAN or parallel C compliers, which are just traditional sequential FORTRAN or C compilers expanded with communication statements. Programmers suffer from writing parallel programs with communication statements.The Shared Variable Oriented Parallel Precompiler (SVOPP) proposed in this paper can automatically generate appropriate communication statements based on shared variables for SPMD (Single Program Multiple Data) computa-tion model and greatly ease the parallel programming with high communication efficiency. The core function of parallel C precompi1er has been successfully veri-fied on a transputer-based parallel computer. Its prominent performance shows that SVOPP is probably a break-through in parallel programming technique.展开更多
摘要An object-oriented C++ parallel compiler System, called OOCPCS, is developed to facilitate programmers to write sequential programs using C++ or Annotated C++ language for parallel computahon. OOCPCS bases on an integrated object-oriented paradigm and large-grain data flow model, called OOLGDFM, and recognizes automatically parallel objects using parallel compiling techniques. The paper describes the object-oriented parallel model and realization of the System on networks.
摘要A systolic array architecture computer (FXCQ) has been designed for signal processing. R can handle floating point data at very high speed. It is composed of 16 processing cells and a cache that are connected linearly and form a ring structure. All processing cells are identical and programmable. Each processing cell has the peak performance of 20 million floating-point operations per second (20MFLOPS). The machine therefore has a peak performance of 320 M FLOPS. It is integrated as an attached processor into a host system through VME bus interface. Programs for FXCQ are written in a high-level language -B language, which is supported by a parallel optimizing compiler. This paper describes the architecture of FXCQ, B language and its compiler.
摘要An object-oriented approach is taken to the problem of formulating portable, easy-to-modify PDE solvers for realistic problems in three space dimensions. The resulting software library, Cogito, contains tools for writing programs to be executed on MIMD computers with distributed memory. Difference methods on composite, structured grids are supported. Most of the Cogito classes have been implemented in Fortran 77, in such a way that the object-oriented design is visible. With respect to parallel performance, these tools yield code that is comparable to parallel solvers written in plain Fortran 77. The resulting programs are can be executed without modification on a large number of multicomputer platforms, and also on serial computers. The uppermost level of abstraction in Cogito concerns the problem of decoupling the numerical method from the PDE problem. The validity of these tools has been preliminarily demonstrated with a C++ implementation for one-dimensional problems.
基金Supported by the National Key Research and Development Project of China(No.2020AAA0104603)the National Natural Science Foundation of China(No.61834005,61772417)the Shaanxi Province Key R&D Plan(No.2021GY-029).
摘要To improve the inference efficiency of convolutional neural networks(CNN),the existing neural networks mainly adopt heuristic and dynamic programming algorithms to realize parallel scheduling among operators.Heuristic scheduling algorithms can generate local optima easily,while the dynamic programming algorithm has a long convergence time for complex structural models.This paper mainly studies the parallel scheduling between operators and proposes an inter-operator parallelism schedule(IOPS)scheduling algorithm that guarantees the minimum similar execution delay.Firstly,a graph partitioning algorithm based on the largest block is designed to split the neural network model into multiple subgraphs.Then,the operators that meet the conditions is replaced according to the defined operator replacement rules.Finally,the optimal scheduling method based on backtracking is used to schedule the computational graph.Network models such as Inception-v3,ResNet-50,and RandWire are selected for testing.The experimental results show that the algorithm designed in this paper can achieve a 1.6×speedup compared with the existing sequential execution methods.
基金supported by the research funding KYQD(ZR)1974 from Hainan University.
摘要The currently available compilation techniques are for general computing and are not optimized for physical layer computing in 5G micro base stations.In such cases,the foreseeable data sizes and small code size are application specific opportunities for baseband algorithm optimizations.Therefore,the special attention can be paid,for example,the specific register allocation algorithm has not been studied so far.The compilation for kernel sub-routines of baseband in 5G micro base stations is our focusing point.For applications of known and fixed data size,we proposed a compilation scheme of parallel data accessing,while operands can be mainly allocated and stored in registers.Based on a small register group(48×32b),the target of our compilation scheme is the optimization of baseband algorithms based on 4×4 or smaller matrices,maximizing the utilization of register files,and eliminating the extra register data exchanging.Meanwhile,when data is allocated into register files,we used VLIW(Very Long Instruction Word)machine to hide the time of data accessing and minimize the cost of data accessing,thus the total execution time is minimum.Experiments indicate that for algorithms with small data size,the cost of data accessing and extra addressing can be minimized.
摘要At present, there are some static code analyses and optimizations that can be applied to Concurrent C programs to improve their performance or verify their logical correctness. These analyses and optimizations are inter-process. In order to make their implementation easy, we propose a new method to construct an optimizing compiling system CCOC for Concurrent C. CCOC supports inter-process code analysis and optimization to Concurrent C programs and does not affect the system's portability and separate compilation of source programs. We also discuss some implementation details of CCOC briefly.
摘要For the moment, commercial parallel computer systems with distributed memory architecture are usually provided with parallel FORTRAN or parallel C compliers, which are just traditional sequential FORTRAN or C compilers expanded with communication statements. Programmers suffer from writing parallel programs with communication statements.The Shared Variable Oriented Parallel Precompiler (SVOPP) proposed in this paper can automatically generate appropriate communication statements based on shared variables for SPMD (Single Program Multiple Data) computa-tion model and greatly ease the parallel programming with high communication efficiency. The core function of parallel C precompi1er has been successfully veri-fied on a transputer-based parallel computer. Its prominent performance shows that SVOPP is probably a break-through in parallel programming technique.