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NeuroPulse:Spiking-Transformer Hybrid Architecture for Ultra-Low-Power Continual Learning in Neuromorphic Network Processors 认领 引用
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作者 Mohammed Abdullah Alsuwaiket 《Computers, Materials & Continua》 SCIE EI 2026年第9期1735-1757,共23页
Conventional deep learning networks impose prohibitive energy requirements on continuously operational network intelligence applications such as anomaly detection,traffic classification,and adaptive Quality-of-Service... Conventional deep learning networks impose prohibitive energy requirements on continuously operational network intelligence applications such as anomaly detection,traffic classification,and adaptive Quality-of-Service(QoS)control.This paper proposes NeuroPulse,a spiking-transformer hybrid neural architecture that combines the temporal sparsity of spiking neural networks(SNNs)with the representational power of sparse self-attention,enabling efficient deployment on neuromorphic network processors(NNPs).We propose a Rate-Coded Cross-Attention(RCCA)module,which converts population-coded spike-trains into attention queries,allowing long-range dependency modeling within sub-milliwatt(sub-mW)power budgets.NeuroPulse also supports catastrophe-free continual learning on non-stationary network traffic distributions via a Hebbian Synaptic Consolidation(HSC)mechanism,eliminating the need for full model retraining.Experiments on NSL-KDD,UNSW-NB15,and real-world 5G RAN telemetry datasets demonstrate that NeuroPulse achieves 94.3%intrusion detection accuracy at 0.23 mW average energy consumption—a 12×power reduction over transformer-only baselines—while retaining 97.1%of accumulated knowledge after 50 sequential task updates,making it uniquely suited for always-on intelligent network nodes. 展开更多
关键词 Spiking neural networks neuromorphic computing sparse self-attention continuous learning intrusion detection energy efficient AI network processors
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Zuchongzhi-3 Sets New Benchmark with 105-Qubit Superconducting Quantum Processor 认领 引用
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作者 LIU Danxu GE Shuyun WU Yuyang 《Bulletin of the Chinese Academy of Sciences》 2025年第1期55-56,共2页
A team of researchers from the University of Science and Technology of China(USTC)of the Chinese Academy of Sciences(CAS)and its partners have made significant advancements in random quantum circuit sampling with Zuch... A team of researchers from the University of Science and Technology of China(USTC)of the Chinese Academy of Sciences(CAS)and its partners have made significant advancements in random quantum circuit sampling with Zuchongzhi-3,a superconducting quantum computing prototype featuring 105 qubits and 182 couplers. 展开更多
关键词 quantum circuit sampling superconducting quantum computing prototype zuchongzhi superconducting quantum processor qubits couplers
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基于PowerMILL PostProcessor的海德汉iTNC530系统PLANE指令后置处理研究 认领 引用
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作者 康晓崇 《机械研究与应用》 2025年第5期102-107,共6页
后置处理在计算机辅助制造(CAM)与数控加工之间起到关键的桥梁作用,其性能直接影响加工精度和效率。该文基于PowerMILL后处理编辑器开发了一个针对海德汉iTNC530系统的后处理器,旨在实现PLANE指令的自动生成,以适应复杂的多轴加工任务... 后置处理在计算机辅助制造(CAM)与数控加工之间起到关键的桥梁作用,其性能直接影响加工精度和效率。该文基于PowerMILL后处理编辑器开发了一个针对海德汉iTNC530系统的后处理器,旨在实现PLANE指令的自动生成,以适应复杂的多轴加工任务。文章详细描述了开发流程,包括刀具方向向量的提取、旋转角度的计算以及PLANE指令的生成,并结合具体案例展示了如何应用数学模型与旋转矩阵进行刀具路径的优化控制。仿真验证结果表明,所开发的后置处理器能够生成高精度的数控程序,提高了加工的自动化程度和稳定性,可以为多轴加工中的后置处理开发提供实践指导和技术参考。 展开更多
关键词 后置处理开发 海德汉iTNC530 PLANE指令 数学模型
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A VLIW Architecture Stream Cryptographic Processor for Information Security 认领 引用 被引量：4
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作者 Longmei Nan Xuan Yang +4 位作者 Xiaoyang Zeng Wei Li Yiran Du Zibin Dai Lin Chen 《China Communications》 SCIE CSCD 2019年第6期185-199,共15页
As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they ... As an important branch of information security algorithms,the efficient and flexible implementation of stream ciphers is vital.Existing implementation methods,such as FPGA,GPP and ASIC,provide a good support,but they could not achieve a better tradeoff between high speed processing and high flexibility.ASIC has fast processing speed,but its flexibility is poor,GPP has high flexibility,but the processing speed is slow,FPGA has high flexibility and processing speed,but the resource utilization is very low.This paper studies a stream cryptographic processor which can efficiently and flexibly implement a variety of stream cipher algorithms.By analyzing the structure model,processing characteristics and storage characteristics of stream ciphers,a reconfigurable stream cryptographic processor with special instructions based on VLIW is presented,which has separate/cluster storage structure and is oriented to stream cipher operations.The proposed instruction structure can effectively support stream cipher processing with multiple data bit widths,parallelism among stream cipher processing with different data bit widths,and parallelism among branch control and stream cipher processing with high instruction level parallelism;the designed separate/clustered special bit registers and general register heaps,key register heaps can satisfy cryptographic requirements.So the proposed processor not only flexibly accomplishes the combination of multiple basic stream cipher operations to finish stream cipher algorithms.It has been implemented with 0.18μm CMOS technology,the test results show that the frequency can reach 200 MHz,and power consumption is 310 mw.Ten kinds of stream ciphers were realized in the processor.The key stream generation throughput of Grain-80,W7,MICKEY,ACHTERBAHN and Shrink algorithm is 100 Mbps,66.67 Mbps,66.67 Mbps,50 Mbps and 800 Mbps,respectively.The test result shows that the processor presented can achieve good tradeoff between high performance and flexibility of stream ciphers. 展开更多
关键词 stream cipher VLIW architecture processor reconfigurable application-specific instruction-set
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Tunable microwave signal generation based on an Opto-DMD processor and a photonic crystal fiber 认领 引用 被引量：3
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作者 王涛 桑新柱 +12 位作者 颜玢玢 艾琪 李妍 陈笑 张颖 陈根祥 宋菲君 张霞 王葵如 苑金辉 余重秀 肖峰 Alameh Kamal 《Chinese Physics B》 SCIE EI CAS CSCD 2014年第6期304-310,共7页
Frequency-tunable microwave signal generation is proposed and experimentally demonstrated with a dual-wavelength single-longitudinal-mode （SLM） erbium-doped fiber ring laser based on a digital Opto-DMD processor and... Frequency-tunable microwave signal generation is proposed and experimentally demonstrated with a dual-wavelength single-longitudinal-mode （SLM） erbium-doped fiber ring laser based on a digital Opto-DMD processor and four-wave mixing （FWM） in a high-nonlinear photonic crystal fiber （PCF）. The high-nonlinear PCF is employed for the generation of the FWM to obtain stable and uniform dual-wavelength oscillation. Two different short passive sub-ring cavities in the main ring cavity serve as mode filters to make SLM lasing. The two lasing wavelengths are electronically selected by loading different gratings on the Opto-DMD processor controlled with a computer. The wavelength spacing can be smartly adjusted from 0.165 nm to 1.08 nm within a tuning accuracy of 0.055 nm. Two microwave signals at 17.23 GHz and 27.47 GHz are achieved. The stability of the microwave signal is discussed. The system has the ability to generate a 137.36-GHz photonic millimeter signal at room temperature. 展开更多
关键词 fiber lasers four-wave mixing Opto-DMD processor tunable microwave signal
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A Reconfigurable Block Cryptographic Processor Based on VLIW Architecture 认领 引用 被引量：12
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作者 LI Wei ZENG Xiaoyang +2 位作者 NAN Longmei CHEN Tao DAI Zibin 《China Communications》 SCIE CSCD 2016年第1期91-99,共9页
An Efficient and flexible implementation of block ciphers is critical to achieve information security processing.Existing implementation methods such as GPP,FPGA and cryptographic application-specific ASIC provide the... An Efficient and flexible implementation of block ciphers is critical to achieve information security processing.Existing implementation methods such as GPP,FPGA and cryptographic application-specific ASIC provide the broad range of support.However,these methods could not achieve a good tradeoff between high-speed processing and flexibility.In this paper,we present a reconfigurable VLIW processor architecture targeted at block cipher processing,analyze basic operations and storage characteristics,and propose the multi-cluster register-file structure for block ciphers.As for the same operation element of block ciphers,we adopt reconfigurable technology for multiple cryptographic processing units and interconnection scheme.The proposed processor not only flexibly accomplishes the combination of multiple basic cryptographic operations,but also realizes dynamic configuration for cryptographic processing units.It has been implemented with0.18μm CMOS technology,the test results show that the frequency can reach 350 MHz.and power consumption is 420 mw.Ten kinds of block and hash ciphers were realized in the processor.The encryption throughput of AES,DES,IDEA,and SHA-1 algorithm is1554 Mbps,448Mbps,785 Mbps,and 424 Mbps respectively,the test result shows that our processor's encryption performance is significantly higher than other designs. 展开更多
关键词 Block Cipher VLIW processor reconfigurable application-specific instruction-set
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Three Dimensional Simulation of Ion Thruster Plume-Spacecraft Interaction Based on a Graphic Processor Unit 认领 引用 被引量：2
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作者 任军学 李娟 +3 位作者 谢侃 田华兵 仇钎 汤海滨 《Plasma Science and Technology》 SCIE EI CAS CSCD 2013年第7期702-709,共8页
Based on the three-dimensional particle-in-cell （PIC） method and Compute Unified Device Architecture （CUDA）, a parallel particle simulation code combined with a graphic processor unit （GPU） has been developed fo... Based on the three-dimensional particle-in-cell （PIC） method and Compute Unified Device Architecture （CUDA）, a parallel particle simulation code combined with a graphic processor unit （GPU） has been developed for the simulation of charge-exchange （CEX） xenon ions in the plume of an ion thruster. Using the proposed technique, the potential and CEX plasma distribution are calculated for the ion thruster plume surrounding the DS1 spacecraft at different thrust levels. The simulation results are in good agreement with measured CEX ion parameters reported in literature, and the CPU＇s results are equal to a CPU＇s. Compared with a single CPU Intel Core 2 E6300, 16-processor GPU NVIDIA GeForce 9400 GT indicates a speedup factor of 3.6 when the total macro particle number is 1.1 × 10^6. The simulation results also reveal how the back flow CEX plasma affects the spacecraft floating potential, which indicates that the plume of the ion thruster is indeed able to alleviate the extreme negative floating potentials of spacecraft in geosynchronous orbit. 展开更多
关键词 ion thruster particle simulation graphic processor uait plume
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Speeding up the MATLAB complex networks package using graphic processors 认领 引用 被引量：2
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作者 张百达 唐玉华 +1 位作者 吴俊杰 李鑫 《Chinese Physics B》 SCIE EI CAS CSCD 2011年第9期460-467,共8页
The availability of computers and communication networks allows us to gather and analyse data on a far larger scale than previously. At present, it is believed that statistics is a suitable method to analyse networks ... The availability of computers and communication networks allows us to gather and analyse data on a far larger scale than previously. At present, it is believed that statistics is a suitable method to analyse networks with millions, or more, of vertices. The MATLAB language, with its mass of statistical functions, is a good choice to rapidly realize an algorithm prototype of complex networks. The performance of the MATLAB codes can be further improved by using graphic processor units （GPU）. This paper presents the strategies and performance of the GPU implementation of a complex networks package, and the Jacket toolbox of MATLAB is used. Compared with some commercially available CPU implementations, GPU can achieve a speedup of, on average, 11.3x. The experimental result proves that the GPU platform combined with the MATLAB language is a good combination for complex network research. 展开更多
关键词 complex networks graphic processors unit MATLAB Jacket Toolbox
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Design of a clustered data-driven array processor for computer vision 认领 引用 被引量：2
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作者 Shan Rui Deng Junyong +3 位作者 Jiang Lin Zhu Yun Wu Haoyue He Feilong 《High Technology Letters》 EI CAS 2020年第4期424-434,共11页
Computer vision(CV)is widely expected to be the next big thing in emerging applications.So many heterogeneous architectures for computer vision emerge.However,plenty of data need to be transferred between different st... Computer vision(CV)is widely expected to be the next big thing in emerging applications.So many heterogeneous architectures for computer vision emerge.However,plenty of data need to be transferred between different structures for heterogeneous architecture.The long data transfer delay becomes the mainly problem to limit the processing speed for computer vision applications.For reducing data transfer delay and fasting computer vision applications,a clustered data-driven array processor is proposed.A three-level pipelining processing element is designed which supports two-buffer data flow interface and 8 bits,16 bits,32 bits subtext parallel computation.At the same time,for accelerating transcendental function computation,a four-way shared pipelining transcendental function accelerator is designed,which is based on Y-intercept adjusted piecewise linear segment algorithm.A distributed shared memory structure based on unified addressing is also employed.To verify efficiency of architecture,some image processing algorithms are implemented on proposed architecture.Simultaneously the proposed architecture has been implemented on Xilinx ZC 706 development board.The same circuitry has been synthesized using SMIC 130 nm CMOS technology.The circuitry is able to run at 100 MHz.Area is 26.58 mm2. 展开更多
关键词 array processor data-driven adjacent interconnection distributed memory computer vision(CV)
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Experimentation of a 1-pixel bit reconfigurable ternary optical processor 认领 引用 被引量：5
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作者 王宏健 金翊 +1 位作者 欧阳山 周裕 《Journal of Shanghai University(English Edition)》 2011年第5期430-436,共7页
A detailed experiment of 1-pixel bit reconfigurable ternary optical processor （TOP） is proposed in the paper. 42 basic operation units （BOUs） and 28 typical logic operators of the TOP are realized in the experimen... A detailed experiment of 1-pixel bit reconfigurable ternary optical processor （TOP） is proposed in the paper. 42 basic operation units （BOUs） and 28 typical logic operators of the TOP are realized in the experiment. Results of the test cases elaborately cover the every combination of BOUs and all the nine inputs of ternary processor. Both the experiment process and results analysis are given in this paper. The experimental results demonstrate that the theory of reconfiguring a TOP is valid and that the reconfiguration circuitry is effective. 展开更多
关键词 ternary optical processor （TOP） decrease-radix design basic operation units （BOUs） reconfigurability recon figuration circuitry
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The history of CochlearTM Nucleus~ sound processor upgrades:30 years and counting 认领 引用 被引量：2
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作者 Anne L.Beiter Esti Nel 《Journal of Otology》 CAS CSCD 2015年第3期108-114,共7页
Objective:To review developments in sound processors over the past 30 years that have resulted in significant improvements in outcomes for Nucleus~ recipients.
关键词 Cochlear implant Sound processor SmartSound SCAN Wireless accessories
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MICROTHREAD BASED (MTB) COARSE GRAINED FAULT TOLERANCE SUPERSCALAR PROCESSOR ARCHITECTURE 认领 引用 被引量：3
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作者 Fu Zhongchuan Chen Hongsong Cui Gang 《Journal of Electronics(China)》 2006年第3期461-466,共6页
Fault tolerance in microprocessor systems has become a popular topic of architecture research. Much work has been done at different levels to accomplish reliability against soft errors, and some fault tolerance archit... Fault tolerance in microprocessor systems has become a popular topic of architecture research. Much work has been done at different levels to accomplish reliability against soft errors, and some fault tolerance architectures have been proposed. But little attention is paid to the thread level superscalar fault tolerance. This letter introduces microthread concept into superscalar processor fault tolerance domain, and puts forward a novel fault tolerance architecture, namely, MicroThread Based (MTB) coarse grained transient fault tolerance superscalar processor architecture, then discusses some detailed implementations. 展开更多
关键词 Microthread Basic block Coarse grained fault tolerance Superscalar processor
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Implementation of a kind of FPGA-based binary phase coded radar signal processor architecture 认领 引用 被引量：1
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作者 田黎育 孙密 万阳良 《Journal of Beijing Institute of Technology》 EI CAS 2012年第4期526-531,共6页
A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules： radar system timer, binary phase coded pulse compression（PC... A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules： radar system timer, binary phase coded pulse compression（PC）, moving target detection （MTD）, constant false alarm rate （CFAR） and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios I! CPU is used for target dots combination and false sidelobe target removing. Sys- tem on programmable chip （SOPC） technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simula- tion result is given. 展开更多
关键词 field programmable gate array（FPGA） radar signal processor system on programma-ble chip （SOPC） binary phase coded
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A two-stage flexible flow-shop scheduling problem with m identical parallel machines on one stage and a batch processor on the other stage 认领 引用 被引量：1
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作者 何龙敏 孙世杰 程明宝 《Journal of Harbin Institute of Technology(New Series)》 EI CAS 2008年第5期674-678,共5页
This paper considers a hybrid two-stage flow-shop scheduling problem with m identical parallel machines on one stage and a batch processor on the other stage. The processing time of job Jj on any of m identical parall... This paper considers a hybrid two-stage flow-shop scheduling problem with m identical parallel machines on one stage and a batch processor on the other stage. The processing time of job Jj on any of m identical parallel machines is aj≡a （j∈N）, and the processing time of job Jj is bj（j∈N） on a batch processorM. We take makespan （Cmax） as our minimization objective. In this paper, for the problem of FSMP-BI （m identical parallel machines on the first stage and a batch processor on the second stage）, based on the algorithm given by Sung and Choung for the problem of 1 ｜ri, BI｜Cmax under the constraint of the given processing sequence, we develop an optimal dynamic programming Algorithm H1 for it in max {O（nlogn）, O（nB）} time. A max {O（nlogn） , O（nB）}time symmetric Algorithm H2 is given then for the problem of BI-FSMP （a batch processor on the first stage and m identical parallel machines on the second stage）. 展开更多
关键词 scheduling flexible flow-shop parallel machines batch processor optimal algorithm
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Trends of Communication Processors 认领 引用 被引量：1
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作者 LIU Dake CAI Zhaoyun WANG Wei 《China Communications》 SCIE CSCD 2016年第1期1-16,共16页
Processors have been playing important roles in both communication infrastructure systems and terminals.In this paper,both application specific and general purpose processors for communications are discussed including... Processors have been playing important roles in both communication infrastructure systems and terminals.In this paper,both application specific and general purpose processors for communications are discussed including the roles,the history,the current situations,and the trends.One trend is that ASIPs(Application Specific Instruction-set Processors) are taking over ASICs(Application Specific Integrated Circuits) because of the increasing needs both on performance and compatibility of multi-modes.The trend opened opportunities for researchers crossing the boundary between communications and computer architecture.Another trend is the serverlization,i.e.,more infrastructure equipments are replaced by servers.The trend opened opportunities for researchers working towards high performance computing for communication,such as research on communication algorithm kernels and real time programming methods on servers. 展开更多
关键词 ASIP baseband processor network processor application processor server processor
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A hybrid two-stage fexible flowshop scheduling problem with m identical parallel machines and a burn-in processor separately 认领 引用 被引量：1
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作者 何龙敏 孙世杰 《Journal of Shanghai University(English Edition)》 2007年第1期33-38,共6页
A hybrid two-stage flowshop scheduling problem was considered which involves m identical parallel machines at Stage 1 and a burn-in processor M at Stage 2, and the makespan was taken as the minimization objective. Thi... A hybrid two-stage flowshop scheduling problem was considered which involves m identical parallel machines at Stage 1 and a burn-in processor M at Stage 2, and the makespan was taken as the minimization objective. This scheduling problem is NP-hard in general. We divide it into eight subcases. Except for the following two subcases： （1） b≥ an, max{m, B} 〈 n; （2） a1 ≤ b ≤ an, m ≤ B 〈 n, for all other subcases, their NP-hardness was proved or pointed out, corresponding approximation algorithms were conducted and their worst-case performances were estimated. In all these approximation algorithms, the Multifit and PTAS algorithms were respectively used, as the jobs were scheduled in m identical parallel machines. 展开更多
关键词 scheduling flexiable flowshop identical machine batch processor complexity approximation algorithm
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Reconfigurable Communication Processor: A New Approach for Network Processor 认领 引用
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作者 孙华 陈青山 张文渊 《Journal of Shanghai Jiaotong university(Science)》 2003年第1期43-47,共5页
As the traditional RISC+ASIC/ASSP approach for network processor design can not meet the today’s requirements, this paper described an alternate approach, Reconfigurable Processing Architecture, to boost the performa... As the traditional RISC+ASIC/ASSP approach for network processor design can not meet the today’s requirements, this paper described an alternate approach, Reconfigurable Processing Architecture, to boost the performance to ASIC level while reserve the programmability of the traditional RISC based system. This paper covers both the hardware architecture and the software development environment architecture. 展开更多
关键词 network processor reconfigurable processor run time reconfiguration field programmable gate array (FPGA) raduced instruction set circuit (RISC) application specific integrated circuit(ASIC)
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DESIGN OF A SYSTEM SOFTWARE BASED ON A JAVA SOC PROCESSOR 认领 引用 被引量：1
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作者 Chen Zhirui Lin Chunyou Tan Hongzhou 《Journal of Electronics(China)》 2010年第6期853-859,共7页
Java technology is spreading rapidly all over the world in recent years. It is a popular application development language for its well-encapsulation, platform-independent and high security. There are great amounts of ... Java technology is spreading rapidly all over the world in recent years. It is a popular application development language for its well-encapsulation, platform-independent and high security. There are great amounts of Java games and other gadgets on mobile platforms, as well as on set-up-box systems. As Java applications become more sophisticated, the Java Virtual Machine (JVM) mid-dle-wares in embedded systems are not satisfying, Java-specific chips extend in the market. All existing Java-based system software or Operating System (OS) are used on JVM, they cannot be used on Java processors. It is important to develop a pure Java system software or OS so that embedded systems using Java processors will have great performance in Java applications. This paper presents a set of system software designed for a Java-specified processor VP6K, which is also a System-on-Chip (SoC). This system software includes real-time multitask dispatching, file management, device management, hardware drivers, and infrastructural Application Programming Interface (APIs). According to ex-perimental results, the system software provides interfaces for Java programs to fully handle CPU resource, so that all applications can be executed properly and efficiently. VP6K embedded platform shows its good performance for Java applications when the system software is implemented. 展开更多
关键词 Java processor Operating System (OS) Task scheduling File management Device management
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LOGIC STRUCTURE OF PROGRAMMABLE INSTRUCTIONS FOR JAVA PROCESSORS 认领 引用 被引量：2
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作者 Chen Zhirui Tan Hongzhou 《Journal of Electronics(China)》 2009年第5期711-714,共4页
There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable... There are varieties of embedded systems in the world. It is a big challenge to optimize the instruction sets of System on Chips (SoCs) according to different systems' working environments. The idea of programmable instruction set is an effective method to gain embedded system's re-configurability. This letter presents a logic module for Java processor to be capable of using programmable instruction set. Cost (area, power, and timing) of the module is trivial. Such module is also reusable for other embedded system solutions besides Java systems. 展开更多
关键词 Programmable instructions Java processor System on Chips （SoCs）
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Architecture-level performance/power tradeoff in network processor design 认领 引用
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作者 陈红松 季振洲 胡铭曾 《Journal of Harbin Institute of Technology(New Series)》 EI CAS 2007年第1期45-48,共4页
Network processors are used in the core node of network to flexibly process packet streams. With the increase of performance, the power of network processor increases fast, and power and cooling become a bottleneck. A... Network processors are used in the core node of network to flexibly process packet streams. With the increase of performance, the power of network processor increases fast, and power and cooling become a bottleneck. Architecture-level power conscious design must go beyond low-level circuit design. Architectural power and performance tradeoff should be considered at the same time. Simulation is an efficient method to design modem network processor before making chip. In order to achieve the tradeoff between performance and power, the processor simulator is used to design the architecture of network processor. Using Netbeneh, Commubench benchmark and processor simulator-SimpleScalar, the performance and power of network processor are quantitatively evaluated. New performance tradeoff evaluation metric is proposed to analyze the architecture of network processor. Based on the high performance lnteI IXP 2800 Network processor eonfignration, optimized instruction fetch width and speed ,instruction issue width, instruction window size are analyzed and selected. Simulation resuits show that the tradeoff design method makes the usage of network processor more effectively. The optimal key parameters of network processor are important in architecture-level design. It is meaningful for the next generation network processor design. 展开更多
关键词 network processor design performance/power simulation tradeoff evaluation optimization
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