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Influences of supply voltage on single event upsets and multiple-cell upsets in nanometer SRAM across a wide linear energy transfer range 认领 引用 被引量：1
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作者 Yin-Yong Luo Wei Chen +1 位作者 Feng-Qi Zhang Tan Wang 《Chinese Physics B》 SCIE EI CAS CSCD 2021年第4期596-604,共9页
The influences of reducing the supply voltage on single event upset(SEU) and multiple-cell upset(MCU) in two kinds of 65-nm static random access memories(SRAMs) are characterized across a wide linear energy transfer(L... The influences of reducing the supply voltage on single event upset(SEU) and multiple-cell upset(MCU) in two kinds of 65-nm static random access memories(SRAMs) are characterized across a wide linear energy transfer(LET) range.The results show that the influence of the voltage variation on SEU cross section clearly depends on the LET value which is above heavy ion LET threshold no matter whether the SRAM is non-hardened 6 T SRAM or radiation-hardened double dual interlocked cells(DICE) SRAM.When the LET value is lower than the LET threshold of MCU,the SEU only manifests single cell upset,the SEU cross section increases with the decrease of voltage.The lower the LET value,the higher the SEU sensitivity to the voltage variation is.Lowering the voltage has no evident influence on SEU cross section while the LET value is above the LET threshold of MCU.Moreover,the reduction of the voltage can result in a decrease in the highest-order MCU event cross section due to the decrease of charge collection efficiency of the outer sub-sensitive volume within a certain voltage range.With further scaling the feature size of devices down,it is suggested that the dependence of SEU on voltage variation should be paid special attention to for heavy ions with very low LET or the other particles with very low energy for nanometer commercial off-the-shelf(COTS) SRAM. 展开更多
关键词 supply voltage single event upsets multiple-cell upsets 65-nm SRAM double DICE SRAM
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Stability and performance analysis of a jump linear control system subject to digital upsets 认领 引用 被引量：1
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作者 王蕊 孙辉 马振洋 《Chinese Physics B》 SCIE EI CAS CSCD 2015年第4期6-15,共10页
This paper focuses on the methodology analysis for the stability and the corresponding tracking performance of a closed-loop digital jump linear control system with a stochastic switching signal. The method is applied... This paper focuses on the methodology analysis for the stability and the corresponding tracking performance of a closed-loop digital jump linear control system with a stochastic switching signal. The method is applied to a flight control system. A distributed recoverable platform is implemented on the flight control system and subject to independent digital upsets. The upset processes are used to stimulate electromagnetic environments. Specifically, the paper presents the scenarios that the upset process is directly injected into the distributed flight control system, which is modeled by independent Markov upset processes and independent and identically distributed （IID） processes. A theoretical performance analysis and simulation modelling are both presented in detail for a more complete independent digital upset injection. The specific examples are proposed to verify the methodology of tracking performance analysis. The general analyses for different configurations are also proposed. Comparisons among different configurations are conducted to demonstrate the availability and the characteristics of the design. 展开更多
关键词 stochastic process stability and performance analysis jump linear system digital upsets
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Multiple bit upsets mitigation in memory by using improved hamming codes and parity codes 认领 引用 被引量：1
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作者 祝名 肖立伊 田欢 《Journal of Harbin Institute of Technology(New Series)》 EI CAS 2010年第5期726-730,共5页
This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended ... This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended at the end of data bits,which eliminates the overhead of interspersing the redundancy bits at the encoder and decoder.The reliability of memory is further enhanced by the layout architecture of redundancy bits and data bits.The proposed scheme has been implemented in Verilog and synthesized using the Synopsys tools.The results reveal that the proposed method has about 19% less area penalties and 13% less power consumption comparing with the current two-dimensional error codes,and its latency of encoder and decoder is 63% less than that of Hamming codes. 展开更多
关键词 memory multiple bit upsets improved hamming codes two-dimensional error codes
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Heavy ion energy influence on multiple-cell upsets in small sensitive volumes:from standard to high energies 认领 引用 被引量：1
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作者 Yang Jiao Li-Hua Mo +10 位作者 Jin-Hu Yang Yu-Zhu Liu Ya-Nan Yin Liang Wang Qi-Yu Chen Xiao-Yu Yan Shi-Wei Zhao Bo Li You-Mei Sun Pei-Xiong Zhao Jie Liu 《Nuclear Science and Techniques》 SCIE EI CAS CSCD 2024年第5期109-121,共13页
The 28 nm process has a high cost-performance ratio and has gradually become the standard for the field of radiation-hardened devices.However,owing to the minimum physical gate length of only 35 nm,the physical area o... The 28 nm process has a high cost-performance ratio and has gradually become the standard for the field of radiation-hardened devices.However,owing to the minimum physical gate length of only 35 nm,the physical area of a standard 6T SRAM unit is approximately 0.16μm2,resulting in a significant enhancement of multi-cell charge-sharing effects.Multiple-cell upsets(MCUs)have become the primary physical mechanism behind single-event upsets(SEUs)in advanced nanometer node devices.The range of ionization track effects increases with higher ion energies,and spacecraft in orbit primarily experience SEUs caused by high-energy ions.However,ground accelerator experiments have mainly obtained low-energy ion irradiation data.Therefore,the impact of ion energy on the SEU cross section,charge collection mechanisms,and MCU patterns and quantities in advanced nanometer devices remains unclear.In this study,based on the experimental platform of the Heavy Ion Research Facility in Lanzhou,low-and high-energy heavy-ion beams were used to study the SEUs of 28 nm SRAM devices.The influence of ion energy on the charge collection processes of small-sensitive-volume devices,MCU patterns,and upset cross sections was obtained,and the applicable range of the inverse cosine law was clarified.The findings of this study are an important guide for the accurate evaluation of SEUs in advanced nanometer devices and for the development of radiation-hardening techniques. 展开更多
关键词 28 nm static random access memory(SRAM) Energy effects Heavy ion Multiple-cell upset(MCU) Charge collection Inverse cosine law
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Impact of incident direction on neutron-induced single-bit and multiple-cell upsets in 14 nm FinFET and 65 nm planar SRAMs 认领 引用
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作者 Shao-Hua Yang Zhan-Gang Zhang +9 位作者 Zhi-Feng Lei Yun Huang Kai Xi Song-Lin Wang Tian-Jiao Liang Teng Tong Xiao-Hui Li Chao Peng Fu-Gen Wu Bin Li 《Chinese Physics B》 SCIE EI CAS CSCD 2022年第12期375-381,共7页
Based on the BL09 terminal of China Spallation Neutron Source(CSNS),single event upset(SEU)cross sections of14 nm fin field-effect transistor(FinFET)and 65 nm quad data rate(QDR)static random-access memories(SRAMs)are... Based on the BL09 terminal of China Spallation Neutron Source(CSNS),single event upset(SEU)cross sections of14 nm fin field-effect transistor(FinFET)and 65 nm quad data rate(QDR)static random-access memories(SRAMs)are obtained under different incident directions of neutrons:front,back and side.It is found that,for both technology nodes,the“worst direction”corresponds to the case that neutrons traverse package and metallization before reaching the sensitive volume.The SEU cross section under the worst direction is 1.7-4.7 times higher than those under other incident directions.While for multiple-cell upset(MCU)sensitivity,side incidence is the worst direction,with the highest MCU ratio.The largest MCU for the 14 nm FinFET SRAM involves 8 bits.Monte-Carlo simulations are further performed to reveal the characteristics of neutron induced secondary ions and understand the inner mechanisms. 展开更多
关键词 neutron fin field-effect transistor(FinFET) single event upset(SEU) Monte-Carlo simulation
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Impacts of test factors on heavy ion single event multiple-cell upsets in nanometer-scale SRAM 认领 引用 被引量：2
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作者 罗尹虹 张凤祁 +4 位作者 郭红霞 肖尧 赵雯 丁李利 王园明 《Journal of Semiconductors》 EI CAS CSCD 2015年第11期63-68,共6页
Single event multiple-cell upsets（MCU） increase sharply with the semiconductor devices scaling. The impacts of several test factors on heavy ion single event MCU in 65 nm SRAM are studied based on the buildup of MCU... Single event multiple-cell upsets（MCU） increase sharply with the semiconductor devices scaling. The impacts of several test factors on heavy ion single event MCU in 65 nm SRAM are studied based on the buildup of MCU test data acquiring and processing technique, including the heavy ion LET, the tilt angle, the device orientation, the test pattern and the supply voltage; the MCU physical bitmaps are extracted correspondingly. The dependencies of parameters such as the MCU percentage, MCU mean and topological pattern on these factors are summarized and analyzed. This work is meaningful for developing a more reasonable single event test method and assessing the effectiveness of anti-MCU strategies on nanometer-scale devices. 展开更多
关键词 multiple-cell upsets nanometer-scale SRAM test factors device orientation
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Characterization of single-event multiple cell upsets in a custom SRAM in a 65 nm triple-well CMOS technology 认领 引用 被引量：2
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作者 CHEN HaiYan CHEN JianJun YAO Long 《Science China(Technological Sciences)》 SCIE EI CAS CSCD 2015年第10期1726-1730,共5页
In this paper, the characterization of single event multiple cell upsets(MCUs) in a custom SRAM is performed in a 65 nm triple-well CMOS technology, and O(linear energy transfer(LET) = 3.1 Me V cm2/mg), Ti(LET = 22.2 ... In this paper, the characterization of single event multiple cell upsets(MCUs) in a custom SRAM is performed in a 65 nm triple-well CMOS technology, and O(linear energy transfer(LET) = 3.1 Me V cm2/mg), Ti(LET = 22.2 Me V cm2/mg) and Ge(LET = 37.4 Me V cm2/mg) particles are employed. The experimental results show that the percentage of MCU events in total upset events is 71.11%, 83.47% and 85.53% at O, Ti and Ge exposures. Moreover, due to the vertical well isolation layout, 100%(O), 100%(Ti) and 98.11%(Ge) MCU cluster just present at one or two adjacent columns, but there are still 4 cell upsets in one MCU cluster appearing on the same word wire. The characterization indicates that MCUs have become the main source of soft errors in SRAM, and even though combining the storage array interleaving distance(ID) scheme with the error detection and correction(EDAC) technique, the MCUs cannot be completely eliminated, new radiation hardened by design techniques still need to be further studied. 展开更多
关键词 multiple cell upsets （MCUs） static random access memories （SRAM） vertical well isolation radiation hardened by de-sign
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PHOTO NEWS 认领 引用
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《China Today》 2026年第8期6-15,共10页
Highlights of the 2026 FIFA World Cup This World Cup featured numerous stunning upsets and historic clashes,showcasing spectacular competitive intensity and heartwarming sportsmanship on the pitch.
关键词 historic clashes stunning upsets spectacular competitive intensity competitive intensity heartwarming sportsmanship
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High strength-ductility synergy achieved in low-alloyed Mg alloys via hyper-substructure introduction through upsetting-assisted asymmetric extrusion 认领 引用
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作者 Jin-Long Cai Pei-Lin Liu +2 位作者 Xu Guo Qing Liu Zhi-Gang Li 《Journal of Magnesium and Alloys》 SCIE EI CAS CSCD 2026年第2期310-331,共22页
This study demonstrates that introducing multidimensional crystallographic defects through severe plastic deformation may overcome the strength-ductility trade-off in magnesium alloys.We developed a unique hyper-subst... This study demonstrates that introducing multidimensional crystallographic defects through severe plastic deformation may overcome the strength-ductility trade-off in magnesium alloys.We developed a unique hyper-substructure(HSS)microstructure via novel upsetting-assisted asymmetric extrusion at low temperature(∼220℃).The UE-55 specimen with∼0.34 upsetting strain exhibited exceptional properties:∼266.5 MPa yield strength,∼311.9 MPa ultimate tensile strength,and∼27.6%fracture elongation in a low-alloyed magnesium system(∼3.3 wt.%total alloy content).Remarkably,HSS simultaneously enhances both strength and ductility.Refined grains and elevated dislocation density within HSS primarily strengthen the material.Enhanced plasticity stems from synergistic mechanisms.Pre-existing dislocations multiply during tension through interaction-mediated processes,facilitating c-axis deformation.Simultaneously,linearly aligned low-angle boundaries(LABs)obstruct the propagation of microcracks initiated near high-angle boundaries(HABs)by fractured coarse secondary phases.This significantly improves the material’s microcrack accommodation capacity.This work establishes substructures as primary carriers of plastic deformation,diverging from conventional rapid extrusion techniques that produce fully recrystallized microstructures.The resultant strength-ductility synergy emerges from coordinated strengthening mechanisms.Notably,processing at 20.6 m/min extrusion speed enables efficient fabrication of high-performance magnesium extrudates.Furthermore,analysis of HSS formation mechanisms provides novel insights for industrial-scale production of cost-effective magnesium alloys. 展开更多
关键词 Magnesium alloy Upsetting strain Asymmetric extrusion Hyper-substructure
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Effect of pre-heat treatment and subsequent ECAP-CU on microstructure and corrosion behavior of 7075 Al alloy fasteners 认领 引用
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作者 ZHANG Jun-jie HE Tao +4 位作者 DU Xiang-yang ALEXER Vereschaka SONG Miao CHEN Xi-lin LI Jian 《Journal of Central South University》 SCIE EI CAS CSCD 2025年第7期2383-2403,共21页
It is of great significance to study the corrosion process of aluminum(Al)alloys fasteners in order to mitigate corrosion for their widespread applications.In this paper,a method for enhancing the corrosion resistance... It is of great significance to study the corrosion process of aluminum(Al)alloys fasteners in order to mitigate corrosion for their widespread applications.In this paper,a method for enhancing the corrosion resistance of Al alloy fasteners is proposed.7075 Al alloy parts with a fine-grained microstructure were prepared by pre-heat treatment(PHT),combined subsequent equal channel angular pressing(ECAP)and cold upsetting(CU).The corrosion behavior of the specimens was investigated by intergranular corrosion and electrochemical test.Microstructure investigations were carried out by field emission scanning electron microscopy,energy dispersive spectrometer and transmission electron microscopy.The relationship between microstructural evolution and corrosion resistance changes was also explored.The results show that both PHT and ECAP-CU significantly improved the corrosion resistance of the samples and modified the corrosion process.The open circuit potential,corrosion current density and corrosion rate of the alloy on electrochemical test were(-0.812±8.854)×10-5 V(vs.SCE),(6.379±0.025)×10-6 A/cm2 and 0.066 mm/year,respectively,and the intergranular corrosion depth was(557±8)μm.The main factor controlling the corrosion behavior was the microstructure evolution.After PHT,the disappearance of the dendritic structure and the dissolution of the nonequilibrium second phase eliminated the potential difference between the phases,reducing the free energy in the as cast state.When ECAP-CU was used after PHT,the grain refinement was accompanied by a high density of grain boundaries and dislocations,which led to the formation of a denser passivation film on the alloy surface,improving the corrosion resistance in an aggressive environment. 展开更多
关键词 aluminum alloy fasteners heat treatment equal channel angular pressing cold upsetting microstructure corrosion resistance
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Back-gate bias and supply voltage dependency on the single-event upset susceptibility of 6 T CSOI-SRAM 认领 引用
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作者 Li-Wen Yao Jin-Hu Yang +12 位作者 Yu-Zhu Liu Bo Li Yang Jiao Shi-Wei Zhao Qi-Yu Chen Xin-Yu Li Tian-Qi Wang Fan-Yu Liu Jian-Tou Gao Jian-Li Liu Xing-Ji Li Jie Liu Pei-Xiong Zhao 《Nuclear Science and Techniques》 SCIE EI CAS CSCD 2025年第9期105-115,共11页
This paper explores the impact of back-gate bias (Vsoi) and supply voltage (VDD) on the single-event upset (SEU) cross section of 0.18μm configurable silicon-on-insulator static random-access memory (SRAM) unde... This paper explores the impact of back-gate bias (Vsoi) and supply voltage (VDD) on the single-event upset (SEU) cross section of 0.18μm configurable silicon-on-insulator static random-access memory (SRAM) under high linear energy transfer heavyion experimentation.The experimental findings demonstrate that applying a negative back-gate bias to NMOS and a positive back-gate bias to PMOS enhances the SEU resistance of SRAM.Specifically,as the back-gate bias for N-type transistors(Vnsoi) decreases from 0 to-10 V,the SEU cross section decreases by 93.23%,whereas an increase in the back-gate bias for P-type transistors (Vpsoi) from 0 to 10 V correlates with an 83.7%reduction in SEU cross section.Furthermore,a significant increase in the SEU cross section was observed with increase in supply voltage,as evidenced by a 159%surge at VDD=1.98 V compared with the nominal voltage of 1.8 V.To explore the physical mechanisms underlying these experimental data,we analyzed the dependence of the critical charge of the circuit and the collected charge on the bias voltage by simulating SEUs using technology computer-aided design. 展开更多
关键词 Single-event upset(SEU) Static random-access memory(SRAM) Back-gate voltage Supply voltage
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Investigation of Heavy Ion Induced Failure Modes of Flash Memory with Error Correct Code 认领 引用
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作者 CHEN Qiyu LIU Jie +7 位作者 YAO Liwen YAN Xiaoyu JIAO Yang LI Xinyu ZHAI Pengfei YE Bing ZHAO Peixiong SUN Youmei 《原子核物理评论》 CAS CSCD 北大核心 2025年第4期749-756,共8页
The Error Correcting Code(ECC)is one of the most used hardening methods in Flash memory.In this study,the effect of ECC failure modes on memory error cross section has been investigated.The errors are counted in the s... The Error Correcting Code(ECC)is one of the most used hardening methods in Flash memory.In this study,the effect of ECC failure modes on memory error cross section has been investigated.The errors are counted in the situations of ECC function enabled and disabled separately after heavy ion irradiation.The results show that the upset cross section is a constant value in different ion fluences when the ECC function is disabled.With the ECC function enabled,the error cross section increases with the increase of ion fluences because the ECC failure modes lead to the increase in the number of errors.Moreover,all ECC failure modes are simulated,and their probability is calculated separately.The results help to understand the impact of ECC failure modes on Flash memory’s error cross section induced by irradiation.Some possible mitigation approaches are provided in response to this phenomenon. 展开更多
关键词 flash memory single event upset(SEU) heavy ion irradiation error correcting code(ECC) hamming code
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Heavy ion‑induced MCUs in 28nm SRAM‑based FPGAs:upset proportions,classifications,and pattern shapes 认领 引用 被引量：2
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作者 Shuai Gao Xin‑Yu Li +7 位作者 Shi‑Wei Zhao Ze He Bing Ye Li Cai You‑Mei Sun Guo‑Qing Xiao Chang Cai Jie Liu 《Nuclear Science and Techniques》 SCIE EI CAS CSCD 2022年第12期128-137,共10页
For modern scaling devices,multiple cell upsets(MCUs)have become a major threat to high-reliability field-programmable gate array(FPGA)-based systems.Thus,both performing the worst-case irradiation tests to provide th... For modern scaling devices,multiple cell upsets(MCUs)have become a major threat to high-reliability field-programmable gate array(FPGA)-based systems.Thus,both performing the worst-case irradiation tests to provide the actual MCU response of devices and proposing an effective MCU distinction method are urgently needed.In this study,high-and medium-energy heavy-ion irradiations for the configuration random-access memory of 28 nm FPGAs are performed.An MCU extraction method supported by theoretical predictions is proposed to study the MCU sizes,shapes,and frequencies in detail.Based on the extraction method,the different percentages,and orientations of the large MCUs in both the azimuth and zenith directions determine the worse irradiation response of the FPGAs.The extracted largest 9-bit MCUs indicate that high-energy heavy ions can induce more severe failures than medium-energy ones.The results show that both the use of high-energy heavy ions during MCU evaluations and effective protection for the application of high-density 28 nm FPGAs in space are extremely necessary. 展开更多
关键词 FPGAs Heavy ions Multiple cell upsets Extraction Worse irradiation
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Radiation Tolerant Viterbi Decoders for On-Board Processing(OBP) in Satellite Communications 认领 引用 被引量：1
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作者 Zhen Gao Lina Yan +3 位作者 Jinhua Zhu Ruishi Han Ullah Anees Reviriego Pedro 《China Communications》 SCIE CSCD 2020年第1期140-150,共11页
Modern satellite communication systems require on-board processing(OBP)for performance improvements,and SRAM-FPGAs are an attractive option for OBP implementation.However,SRAM-FPGAs are sensitive to radiation effects,... Modern satellite communication systems require on-board processing(OBP)for performance improvements,and SRAM-FPGAs are an attractive option for OBP implementation.However,SRAM-FPGAs are sensitive to radiation effects,among which single event upsets(SEUs)are important as they can lead to data corruption and system failure.This paper studies the fault tolerance capability of a SRAM-FPGA implemented Viterbi decoder to SEUs on the user memory.Analysis and fault injection experiments are conducted to verify that over 97%of the SEUs on user memory would not lead to output errors.To achieve a better reliability,selective protection schemes are then proposed to further improve the reliability of the decoder to SEUs on user memory with very small overhead.Although the results are obtained for a specific FPGA implementation,the developed reliability estimation model and the general conclusions still hold for other implementations. 展开更多
关键词 viterbi decoder on-board processing FPGA user memory fault tolerance single event upsets
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Fault Tolerant Reconfigurable System with Dual-Module Redundancy and Dynamic Reconfiguration 认领 引用 被引量：2
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作者 Qi-Zhong Zhou Xuan Xie +2 位作者 Jing-Chen Nan Yong-Le Xie Shu-Yan Jiang 《Journal of Electronic Science and Technology》 CAS 2011年第2期167-173,共7页
To handle the effects of single event upsets（SEU）,which are common to computers in space radiation environment,a new fault-tolerant system with dual-module redundancy is proposed using dynamic reconfigurable techniq... To handle the effects of single event upsets（SEU）,which are common to computers in space radiation environment,a new fault-tolerant system with dual-module redundancy is proposed using dynamic reconfigurable technique of field programmable gate array（FPGA）. This system contains detection and backup alternative functions,that is,the self-detection and self-healing functions can be completed,and consequently a system design with low hardware redundancy and high resource utilization can be achieved successfully. So it can not only detect fault but also repair the fault effectively after failure. Hence,this method is especially practical to the dynamically reconfigurable computers based on FPGAs. Design methodology has been verified by Virtex-4 FPGA on Xilinx Ml403 development platform. 展开更多
关键词 Dependable computers fault-tolerant field programmable gate array self-detection single event upsets
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Heavy ion-induced single event upset sensitivity evaluation of 3D integrated static random access memory 认领 引用 被引量：8
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作者 Xue-Bing Cao Li-Yi Xiao +5 位作者 Ming-Xue Huo Tian-Qi Wang Shan-Shan Liu Chun-Hua Qi An-Long Li Jin-Xiang Wang 《Nuclear Science and Techniques》 SCIE EI CAS CSCD 2018年第3期31-41,共11页
Heavy ion-induced single event upsets(SEUs)of static random access memory(SRAM), integrated with three-dimensional integrated circuit technology, are evaluated using a Monte Carlo simulation method based on the Geant4... Heavy ion-induced single event upsets(SEUs)of static random access memory(SRAM), integrated with three-dimensional integrated circuit technology, are evaluated using a Monte Carlo simulation method based on the Geant4 simulation toolkit. The SEU cross sections and multiple cell upset(MCU) susceptibility of 3D SRAM are explored using different types and energies of heavy ions.In the simulations, the sensitivities of different dies of 3D SRAM show noticeable discrepancies for low linear energy transfers(LETs). The average percentage of MCUs of 3D SRAM increases from 17.2 to 32.95%, followed by the energy of 209Bi decreasing from 71.77 to 38.28 MeV/u. For a specific LET, the percentage of MCUs presents a notable difference between the face-to-face and back-toface structures. In the back-to-face structure, the percentage of MCUs increases with a deeper die, compared with the face-to-face structure. The simulation method and process are verified by comparing the SEU cross sections of planar SRAM with experimental data. The upset cross sections of the planar process and 3D integrated SRAM are analyzed. The results demonstrate that the 3D SRAM sensitivity is not greater than that of the planar SRAM. The 3D process technology has the potential to be applied to the aerospace and military fields. 展开更多
关键词 3D integration Single event upset (SEU) Multiple cell upset (MCU) Monte Carlo simulation
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Angular dependence of multiple-bit upset response in static random access memories under heavy ion irradiation 认领 引用 被引量：8
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作者 张战刚 刘杰 +9 位作者 侯明东 孙友梅 苏弘 段敬来 莫丹 姚会军 罗捷 古松 耿超 习凯 《Chinese Physics B》 SCIE EI CAS CSCD 2013年第8期529-533,共5页
Experimental evidence is presented relevant to the angular dependences of multiple-bit upset （MBU） rates and patterns in static random access memories （SRAMs） under heavy ion irradiation. The single event upset （... Experimental evidence is presented relevant to the angular dependences of multiple-bit upset （MBU） rates and patterns in static random access memories （SRAMs） under heavy ion irradiation. The single event upset （SEU） cross sections under tilted ion strikes are overestimated by 23.9%-84.6%, compared with under normally incident ion with the equivalent linear energy transfer （LET） value of 41 MeV/（mg/cm2）, which can be partially explained by the fact that the MBU rate for tilted ions of 30° is 8.5%-9.8% higher than for normally incident ions. While at a lower LET of - 9.5 MeV/（mg/cm2）, no clear discrepancy is observed. Moreover, since the ion trajectories at normal and tilted incidences are different, the predominant double-bit upset （DBU） patterns measured are different in both conditions. Those differences depend on the LET values of heavy ions and devices under test. Thus, effective LET method should be used carefully in ground-based testing of single event effects （SEE） sensitivity, especially in MBU-sensitive devices. 展开更多
关键词 single event effects effective LET method multiple-bit upset upset cross section
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Monte Carlo evaluation of spatial multiple-bit upset sensitivity to oblique incidence 认领 引用 被引量：12
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作者 耿超 刘杰 +7 位作者 习凯 张战刚 古松 侯明东 孙友梅 段敬来 姚会军 莫丹 《Chinese Physics B》 SCIE EI CAS CSCD 2013年第5期657-664,共8页
We investigate the impact of heavy ion irradiation on a hypothetical static random access memory （SRAM） device. Influences of the irradiation angle, critical charge, drain-drain spacing, and dimension of device stru... We investigate the impact of heavy ion irradiation on a hypothetical static random access memory （SRAM） device. Influences of the irradiation angle, critical charge, drain-drain spacing, and dimension of device structure on the device sensitivity have been studied. These prediction and simulated results are interpreted with MUFPSA, a Monte Carlo code based on Geant4. The results show that the orientation of ion beams and device with different critical charge exert indis- pensable effects on multiple-bit upsets （MBUs）, and that with the decrease in spacing distance between adjacent cells or the dimension of the cells, the device is more susceptible to single event effect, especially to MBUs at oblique incidence. 展开更多
关键词 Geant4 multiple-bit upset （MBU） critical charge spacing between adjacent cells
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Microstructural evolution and mechanical properties of Mg-9.8Gd-2.7Y-0.4Zr alloy produced by repetitive upsetting 认领 引用 被引量：8
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作者 H.Zhou H.Y.Ning +6 位作者 X.L.Ma D.D.Yin L.R.Xiao X.C.Sha Y.D.Yu Q.D.Wang Y.S.Li 《Journal of Materials Science & Technology》 SCIE EI CAS CSCD 2018年第7期1067-1075,共9页
A newly developed severe plastic deformation （SPD） technique, i.e. repetitive upsetting （RU）, is employed to improve the strength and ductility of a Mg-Gd-Y-Zr alloy. During the RU processing, dynamic recrystalliz... A newly developed severe plastic deformation （SPD） technique, i.e. repetitive upsetting （RU）, is employed to improve the strength and ductility of a Mg-Gd-Y-Zr alloy. During the RU processing, dynamic recrystallization occurs in the Mg alloy, which leads to a significant grain refinement from 11.2 p.m to 2.8 μm. The yield strength （YS）, ultimate tensile strength （UTS） and elongation increase simultaneously with increasing RU passes. The microstructural evolution is affected by processing temperatures. Dynamic recrystallization prevails at low temperatures, while dynamic recovery is the main effect factor at high temperatures. Texture characteristics gradually become random during multiple passes of RU processing, which reduces the tension-compression asymmetry of the Mg-Gd-Y-Zr alloy. 2018 Published by Elsevier Ltd on behalf of The editorial office of Journal of Materials Science ＆ Technology. 展开更多
关键词 Severe plastic deformation （SPD） Repetitive upsetting （RU） Mg-RE alloy Mechanical properties
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Physics-based analysis and simulation model of electromagnetic interference induced soft logic upset in CMOS inverter 认领 引用 被引量：4
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作者 Yu-Qian Liu Chang-Chun Chai +4 位作者 Yu-Hang Zhang Chun-Lei Shi Yang Liu Qing-Yang Fan Yin-Tang Yang 《Chinese Physics B》 SCIE EI CAS CSCD 2018年第6期531-538,共8页
The instantaneous reversible soft logic upset induced by the electromagnetic interference（EMI） severely affects the performances and reliabilities of complementary metal–oxide–semiconductor（CMOS） inverters. This... The instantaneous reversible soft logic upset induced by the electromagnetic interference（EMI） severely affects the performances and reliabilities of complementary metal–oxide–semiconductor（CMOS） inverters. This kind of soft logic upset is investigated in theory and simulation. Physics-based analysis is performed, and the result shows that the upset is caused by the non-equilibrium carrier accumulation in channels, which can ultimately lead to an abnormal turn-on of specific metal–oxide–semiconductor field-effect transistor（MOSFET） in CMOS inverter. Then a soft logic upset simulation model is introduced. Using this model, analysis of upset characteristic reveals an increasing susceptibility under higher injection powers, which accords well with experimental results, and the influences of EMI frequency and device size are studied respectively using the same model. The research indicates that in a range from L waveband to C waveband, lower interference frequency and smaller device size are more likely to be affected by the soft logic upset. 展开更多
关键词 electromagnetic interference soft logic upset non-equilibrium carrier upset model
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